Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-02-25
1998-10-27
Niebling, John
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438229, 438303, 438305, 438306, 438307, H01L 218238
Patent
active
058277617
ABSTRACT:
A method of making NMOS and PMOS devices with different gate lengths includes providing a semiconductor substrate with first and second active regions, forming a first gate over a portion of the first active region and a second gate over a portion of the second active region, wherein the first and second gates are formed in sequence and have different lengths, and forming a source and drain in the first active region and a source and drain in the second active region. Preferably, the first gate is defined by a first photoresist layer patterned with a first exposure time, the second gate is defined by a second photoresist layer patterned with a second exposure time, and the difference in gate lengths is due primarily to a difference between the first and second exposure times.
REFERENCES:
U.S. Patent Application Serial No. 08/623,802, filed Mar. 29, 1996, entitled "Method of Processing a Semiconductor Wafer For Controlling Drive Current", by Fulford, Jr. et al.
Dawson Robert
Fulford Jr. H. Jim
Gardner Mark I.
Hause Frederick N.
Michael Mark W.
Advanced Micro Devices , Inc.
Niebling John
Pham Long
Sigmond David M.
LandOfFree
Method of making NMOS and devices with sequentially formed gates does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of making NMOS and devices with sequentially formed gates, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of making NMOS and devices with sequentially formed gates will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1613429