Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-08-16
2001-09-11
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S291000, C438S302000
Reexamination Certificate
active
06287920
ABSTRACT:
FIELD OF THE INVENTION
The invention is generally related to the field of MOSFET transistors and more specifically to a novel process to achieve multiple threshold voltage integrated circuit transistors.
BACKGROUND OF THE INVENTION
It is often necessary to have transistors with differing threshold voltages on the same integrated circuit. This is mainly used in mixed signal applications but can be used in any integrated circuit application. Currently, a number of implants are performed during transistor fabrication to control the transistor threshold voltage. For the fabrication of integrated circuits containing multiple threshold voltage transistors, this methodology requires multiple photolithography masking steps for each transistor. This adds tremendous cost to the fabrication process as photolithography masking steps are among the most costly processes. There is therefore a great need in the fabrication of integrated circuits for a method to form reliable high performance multiple threshold voltage integrated circuits with a reduction in number of photolithography masking steps over existing methods.
SUMMARY OF THE INVENTION
The instant invention is method for forming multiple threshold voltage transistors on integrated circuits with reduced masks. An embodiment of the invention comprises the steps of: providing a semiconductor substrate region of a first conductivity type; forming a gate dielectric film on said semiconductor substrate region; forming a conductive layer on said gate dielectric; etching said conductive layer to form at least two gate structures over said semiconductor region; implanting said semiconductor region adjacent to said gate structures with a first dopant species of a second conductivity type to form drain extension regions; implanting said semiconductor region adjacent to said gate structures with an angled implant of a second dopant species of a first conductivity type such that said second dopant species impinge on a first side of said gate structures and are shadowed from impinging on a second side of said gate structures said second side of said gate structures being opposite said first side of said gate structures; forming sidewall structures adjacent said first side of said gate structures and said second side of said gate structures; implanting said semiconductor regions adjacent to said sidewall structures with a third dopant species of a second conductivity type to form source and drain regions for at least two transistors; and interconnecting said source and drain regions such that on a first transistor the source region is adjacent to said first side of said gate structure and the drain region is adjacent to said second side of said gate structure and on a second transistor the source region is adjacent to said second side of said gate structure and the drain region is adjacent to said first side of said gate structure.
An advantage of the instant invention is that no masking steps are required for forming the multiple threshold voltage integrated circuits. This and other advantages will be apparent to those of ordinary skill in the art having reference to the specification in conjunction with the drawings.
REFERENCES:
patent: 5432107 (1995-07-01), Uno et al.
patent: 5830788 (1998-11-01), Hiroki et al.
patent: 5834347 (1998-11-01), Fukatsu et al.
patent: 6022778 (2000-02-01), Contiero et al.
patent: 4-329632 (1992-11-01), None
Chatterjee Amitava
Nandakumar Mahalingam
Brady III W. James
Chaudhari Chandra
McLarty Peter K.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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