Method of making metal gate sub-micron MOS transistor

Details Method of making metal gate sub-micron MOS transistor Method of making metal gate sub-micron MOS transistor

1998-01-09

2001-08-14

Lee, Eddie (Department: 2815)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S197000, C438S585000, C438S592000, C438S653000, C438S692000

Reexamination Certificate

active

06274421

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to MOS semiconductor devices and fabrication methods therefor, and specifically to a MOS transistor having an exceptionally thin metal gate therein.
BACKGROUND OF THE INVENTION
A great variety of metal-oxide-semiconductor (MOS) devices are known. It is desirable in such devices to provide a very short channel length in the gate region of the integrated circuit. One way to accomplish this is to use an n
+
or p
+
doped dual polarity polysilicon gate. In the process of forming such a gate, boron or boron compounds are implanted into the substrate, which generally results in the boron compounds penetrating too deep into the substrate. Additionally, the doping density of such compounds must be quite high, otherwise the gate will be depleted which results in a low channel current density.
Chattejee et al, have discussed this problem in connection with a sub-100 nm gate structure formed by replacing polysilicon above a gate region in Sub-100 nm Gate Length Metal Gate NMOS Transistors Fabricated by a Replacement Gate Process, International Electron Devices Meeting, Dec. 7-10, 1997, pp 821-824.
Known metal gate fabrication processes are complicated and pose difficult structural considerations during the fabrication of self-aligned components. For instance, copper makes an ideal metal gate, but it has poor adhesive characteristics as a thin film. Aluminum may also be used as a metal gate, but it is subject to electromigration problems.
SUMMARY OF THE INVENTION
The MOS transistor of the invention is formed on a single crystal silicon substrate doped to form a conductive layer of a first type, and includes: an active region formed on a substrate; a source region and a drain region located in the active region, doped to form conductive channels of a second type; a metal gate region located in the active region between the source region and the drain region, wherein the metal gate has a width of less than one micron; a gate oxide region located over the gate region; an oxide region located over the structure; and a source electrode, a gate electrode and a drain electrode, each connected to their respective regions, and each formed of a combination of a contact metal and an electrode metal. An alternate embodiment includes a pair of MOS transistors which have an interconnect between their gate electrodes and the drain electrode of one transistor and the drain electrode of the other transistor.
An object of the invention is to provide a cost effective method for manufacturing a metal gate sub-micron channel length MOS integrated circuit. Another object of the invention is to provide a metal gate sub-micron channel length MOS integrated circuit which has a high current density.
These and other objects and advantages of the invention will become more fully apparent as the description which follows is read in conjunction with the drawings.


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Article entitled, “Chemical-Mechanical Polishing for Fabricating Patterned W Metal Features as Chip Interconnects”, by Kaufman, et al., published in J. Electrochem. Soc., vol. 138, No. 11, Nov. 1991, pp. 3460-3465.
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