Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Utility Patent
1998-11-04
2001-01-02
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S296000
Utility Patent
active
06168994
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device such as electrically erasable programmable ROM (EEPROM) and a method of manufacturing the same.
2. Description of the Related Art
In recent years, there has been much activity in development of electrically programmable-erasable non-volatile memory devices such as EPROMs or flash memory devices. A low cost and high density flash memory device is being watched. Among flash memories, a flash memory which both writing and erasing are performed by using Fouler Nordheim (F-N) tunneling effect has various advantages compared with another type flash memory.
For example, this type of device can more accelerate writing speed with inner booster circuit due to small power consumption than channel hot electron (CHE) injection type device.
It is well known that as to endurance of writing cycles the F-N tunneling over entire area of channel region has advantage in both writing and erasing.
In a device which write data by extracting electron from control gate using the F-N tunneling, it suffers from the disadvantage of low writing speed with inner circuit due to tunnel current when writing data.
However, a flash memory described above requires high voltage of about 20V when writing, so there it suffers from the disadvantage that it is hard to ensure withstand voltage for inversion and for punch-through in isolation area between memory cells next to each other along a bit line.
In case of isolation of a LOCOS and the like, if thickness of LOCOS would be thicker to ensure withstand voltage for inversion, isolation width would be more wide because the LOCOS is thicker, birds-beak is wider, so integration degree would degrade.
It is possible to use trench isolation instead of the LOCOS. But, to form trench isolation in both area of wide width and narrow width, it needs complex bury and planalization processes such as chemical mechanical planarization (CMP), so cause a problem of raising manufacturing cost.
Further, it is possible to form more heavily doped channel stop. But, to ensure junction voltage, certain isolation area between source-drain region and channel stop ion implantation region is required, so it would degrade integration degree.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor memory device which has short width of element isolation as well as ensuring withstand voltage for inversion and for punch-through.
Another object of the present invention is to provide a method of manufacturing a semiconductor memory device which can manufacture said semiconductor memory device easily and surely avoiding complex process.
According to one aspect of the present invention, there is provided a semiconductor memory device comprising: a substrate, a gate insulating layer formed on the substrate, insulating isolation layers on each side of the gate insulating layer, an impurity diffusion region formed in the substrate beneath the insulating isolation layer, a first conductive layer formed on both the gate insulating layer and the insulating isolation layer, and an element splitting trench which split up at least the insulating isolation layer and the impurity diffusion layer into two parts respectively the substrate and is buried with insulating meterial.
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising the steps of forming a stripe of plural impurity diffusion lines elongated in parallel each other, forming insulating isolation layers on an area of the impurity lines, forming a gate insulating layer in an area between the insulating isolation layers, forming a mask layer covering the gate insulating layer and the insulating isolation layer, forming an anti-etching layer on the mask layer, patterning the anti-etching layer, forming an element splitting trench which splits the impurity diffusion lines to form the source line and the drain line by etching the mask layer, the insulating isolation layer and the substrate successively using the patterned anti-etching layer as a mask, and burying the element splitting trench with insulating material.
Where mask layer is formed for the purpose of protecting the gate insulating layer and the insulating isolation layer when etching a insulating layer formed on and inside the element splitting trench. A mask layer is composed of material having another etching rate to insulating layer for example second conductive layer such as polysilicone.
A semiconductor device of the present invention has a configuration that a first conductive layer exists on a substrate via a gate insulating layer, a diffusion region is formed beneath isolation layers existing on both side of the gate insulating layer, and each device is isolated with insulating splitting trench buried with insulating material (trench isolation) which is dug in a substrate separating and passing through the first conductive layer, the isolation insulating layer and the diffusion layer.
Therefore, since element isolation is provided by trench isolation which has high withstand voltage for inversion and for punch-through, and has short isolation width, a semiconductor device which has improve integration degree ensuring withstand voltage for inversion and for punch-through can be provided. In addition, since trench isolation can be provided in only a memory cell area which needs short isolation width, whereas LOCOS can be provided in a peripheral circuit which needs wide isolation width, a difficult process which plugs wide trench can be avoided and increasing of cost is prevented.
In a manufacturing process of semiconductor device of the present invention, in early stage a source-drain region of devices next to each other which requires element isolation is formed beneath an insulating isolation layer as common wide diffusion region. A first conductive layer covering a gate insulating layer and a insulating isolation layer is patterned and separated. At the same time, using anti-etching layer at this step of process, etching is done through a insulating isolation layer and even a part of substrate in a same pattern, whereby trench is formed on a substrate. This trench separates the wide common diffusion region to form a source line and a drain line.
Therefore, since self-aligned trench isolation which has high withstand for inversion and for punch-through, and provide short isolation width can be formed at the same time as a first conductive layer is patterned, so a device isolation can be produced surely through a very simple process without increasing size of memory cell. In addition, trench isolation can be provided in only a memory cell area which needs short isolation width, whereas LOCOS can be provided in a peripheral circuit which needs wide isolation width, so a difficult process which plugs wide trench can be avoided and increasing of cost is prevented.
REFERENCES:
patent: 5015601 (1991-05-01), Yoshikawa
patent: 5071782 (1991-12-01), Mori
patent: 5150178 (1992-09-01), Mori
patent: 5229631 (1993-07-01), Woo
patent: 5278438 (1994-01-01), Kim et al.
patent: 5306940 (1994-04-01), Yamazaki
patent: 5432112 (1995-07-01), Hong
patent: 5559048 (1996-09-01), Inoue
Chaudhari Chandra
Sonnenschein Nath & Rosenthal
Sony Corporation
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