Method of making memory cell with shallow trench isolation

Details Method of making memory cell with shallow trench isolation Method of making memory cell with shallow trench isolation

1999-11-10

2001-08-14

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S296000

Reexamination Certificate

active

06274434

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a method of manufacturing the same, and particularly relates to a memory cell and a method of manufacturing the same employing an element isolation method for embedding an insulating film into a shallow trench formed in a semiconductor substrate, i.e., employing so-called STI (Shallow Trench Isolation) method.
As a conventional technique, an element isolation method employing STI for using the memory cells on a semiconductor memory device will be described with reference to
FIGS. 14A
to
14
E.
First, as shown in
FIG. 14A
, the surface of a silicon substrate
901
of, for example, a P-type is oxidized (oxide film
911
). At this stage, implantation for forming wells and channels (formation of a channel region) are conducted.
Next, the oxide film
911
is removed and a gate oxide film
904
is formed. At this time, gate oxide films (including those having different thicknesses) for peripheral circuits, not shown, are also formed. Then, a polysilicon
905
, which becomes a floating gate electrode, and a stopper material such as a silicon nitride film
912
are deposited, a resist which is not shown is coated thereon and patterning is conducted. Thereafter, as shown in
FIG. 14B
, using a resist pattern which is not shown as a mask, the silicon nitride film
912
, the polysilicon
905
and the gate oxide film
904
are sequentially subjected to anisotropic etching in this order and then the exposed silicon substrate
901
is anisotropically etched. As a result, a trench
902
is formed in the substrate. The resist pattern which is not shown is then removed off.
Next, as shown in
FIG. 14C
, the inner wall surface of the trench
902
is oxidized so as to ease etching damage (oxide film
913
).
A silicon oxide film
903
of, for example, TEOS (tetraethoxysilane) is deposited on the substrate so as to embed the trench
902
. As shown in
FIG. 14D
, using a chemical mechanical polishing technique or so-called CMP, the surface of the silicon oxide film
903
is flattened. The oxide film
903
is polished off until the surface of the silicon nitride film
912
is exposed.
Finally, as shown in
FIG. 14E
, the silicon nitride film
912
serving as a stopper material is removed, thereby completing element isolation. Thereafter, if a nonvolatile semiconductor memory is to be formed, an ONO film (a layered film of oxide film
itride film/oxide film), a polysilicon layer which becomes a control gate electrode are deposited and patterned into the form of a gate, whereby a memory cell is formed.
As stated above, with the element isolation method in which after the gate oxide film
904
and the gate member
905
are sequentially formed, the gate member
905
, the gate oxide film
904
and the silicon substrate
901
are sequentially etched and in which an STI structure is formed in a self-aligned manner to the gate member
905
, the insulating film embedded in the element isolation region is less likely to be polished off in a later step and good element isolation characteristics can be obtained. This is because, if the element isolation region of STI structure is formed on the silicon substrate and then the gate member is deposited on the silicon substrate through the gate oxide film and patterned, it is necessary at the time of forming the STI structure to remove a covering oxide film having been formed over the semiconductor substrate and to form a new gate oxide film. In that case, the insulating film embedded in the element isolation region is inevitably backed off. The above-stated element isolation method, by contrast, does not include such a covering oxide film removing step (see, for example, Jpn. Pat Appln. KOKAI Publication No. 8-17948).
Meanwhile, it is now assumed that the depth of the trench
902
including the thickness of the CMP stopper material (silicon nitride film
912
) is D
1
and the width of the element isolation region of STI structure is W
1
. If fine processing progresses, the ratio of D
1
to W
1
, i.e. D
1
/W
1
, increases. As a result, the shape of the insulating film (oxide film
903
) embedded as STI structure in the trench by the deposition, becomes worse. For example, due to the processing irregularity for trench widths, the phenomenon that a clearance is formed in the vicinity of the center of the embedded trench occurs. To avoid this, after depositing the oxide film
903
, a high-temperature, long-time thermal step is conducted. Through this step, the trench is formed to be filled up by an insulator without clearances.
As stated above, with the STI structure, if the trench is formed to be filled with the insulator without clearances, a high-temperature, long-time thermal step must be conducted after the deposition of the insulating film (oxide film
903
). According to the manufacturing method for forming the gate oxide film
904
and the like (including gate insulating films for peripheral circuits having different thicknesses) prior to the element region formation step (element isolation step), however, if such a high-temperature, long-time thermal step is conducted, then the gate oxide film deteriorates, diffused layer profile control becomes difficult to make. In this way, reliability of the conventional method is disadvantageously low.
Furthermore, even after a thermal step which is conducted so as not to cause the above-stated reliability-related disadvantages, a depression tends to remain in the upper end portion of the trench. If this depression remains, etching residue is highly likely to remain in the depression when a polysilicon layer or the like which becomes a control gate electrode is deposited and patterned into the form of gate in a later step. If this etching residue remains along the depression, short-circuit may possibly occurs between gates at worst.
BRIEF SUMMARY OF THE INVENTION
The present invention has been achieved in view of the above-stated circumstances. It is, therefore, an object of the present invention to form a trench of STI structure which can make elements smaller in size and realize high integration, into a shape facilitating embedding an insulator into the trench by deposition without generating any clearance, and to thereby provide a highly integrated, highly reliable semiconductor device and a method of manufacturing the same.
A method of manufacturing a semiconductor device according to a first aspect of the present invention, comprises a step of forming a photoresist pattern to cover a predetermined element region on an insulating material layer which is formed on a first gate electrode material layer, the first gate electrode material layer being formed on a first gate insulating film which is formed on a semiconductor substrate; a step of etching the insulating material layer, the first gate electrode material layer, the first gate insulating film and the semiconductor substrate in accordance with the photoresist pattern to form a trench; a step of partially etching the insulating material layer so as to make the insulating material layer smaller in size than at least the element region; and a step of etching the first gate electrode material layer while using the insulating material layer as a mask.
The method of manufacturing a semiconductor device, according to the first aspect of the present invention, may further comprise a step of depositing an insulator over the surface of the semiconductor substrate to embed the insulator in the trench; a step of flattening the insulator deposited over the surface of the semiconductor substrate until a surface of the insulating material layer is exposed; a step of removing the insulating material layer; and a step of patterning the first gate electrode material layer. The method of manufacturing a semiconductor device, may further comprise a step, performed after the step of removing the insulating material layer, of forming a second gate insulating film over the surface of the semiconductor substrate to cover the first gate electrode material layer and the insulator; a step of forming

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