Semiconductor device manufacturing: process – With measuring or testing – Packaging or treatment of packaged semiconductor
Reexamination Certificate
1999-05-11
2001-01-23
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
With measuring or testing
Packaging or treatment of packaged semiconductor
C438S014000, C438S017000, C438S110000, C438S113000, C438S460000, C438S462000
Reexamination Certificate
active
06177288
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to integrated circuit (IC) packages and more specifically to methods for producing and testing chip scale integrated circuit packages.
In the IC packaging industry, there is continuous pressure to reduce the cost of packaging ICs. To accomplish this, a wide variety of package designs and methods for electrically testing these designs have been developed. One of the currently used techniques for producing ICs is referred to as Chip Scale Packaging (CSP).
Chip scale packages are typically produced on panels that include a plurality of packages manufactured on a single panel. FIGS.
1
A-
1
E illustrate the main processing steps used to manufacture typical chip scale packages.
Referring to
FIG. 1A
which illustrates an initial step in producing a plurality of chip scale packages
10
, a panel
12
is provided which includes an array of electrical connecting patterns
14
used to produce chip scale packages
10
. Each of the electrical connecting patterns
14
is associated with one of the chip scale packages
10
being produced. Each of the electrical connecting patterns includes a plurality of electrically conductive traces formed on and/or within panel
12
. As shown in
FIG. 1A
, the electrical connecting patterns are typically electrically connected to one another by traces which extend between adjacent electrical connecting patterns. These traces that interconnect adjacent patterns will be cut to electrically isolate each of the patterns from one another in a later process step in which the panel is sawed into individual chip scale packages.
As illustrated in
FIG. 1B
, a plurality of integrated circuit die
16
are attached to the top surface of panel
12
using a suitable die attaching process. Each die
16
corresponds to an associated one of electrical connecting patterns
14
and is positioned above its associated pattern. Next, as shown in
FIG. 1C
, an array of bonding wires
18
is formed to electrically connect each die
16
to its associated electrical connecting pattern
14
(not shown in FIG.
1
C). Typically, electrical connecting patterns
14
extend through panel
12
such that portions of the pattern are exposed on both the top and the bottom surface of panel
12
. The bonding wires are attached to the portions of the pattern that are exposed on the top surface of the panel using conventional wire bonding processes. The portions of patterns
14
that are exposed on the bottom of panel
12
are used to electrically connect their associated integrated circuit die
16
to external electrical elements once the packages are separated from one another by sawing panel
12
into individual packages.
To protect the die and the arrays of bonding wires, a layer of encapsulating material
20
is applied and cured over the top of panel
12
as shown in FIG.
1
D. In an optional additional step (not shown), arrays of solder balls may be attached to the exposed portions of each of the electrical connecting patterns
14
on the bottom surface of panel
12
. These arrays of solder balls may be used to act as contacts for attaching the package to external electrical elements.
Once panel
12
has been coated with a layer of encapsulating material to protect the die and the bonding wires, packages
10
are singulated by sawing the panel into individual chip scale packages as indicated by dashed saw lines
22
in FIG.
1
E. This step of singulating the packages also electrically isolates each of the packages by cutting any electrical traces of electrical connecting patterns
14
which interconnect adjacent patterns. Once the packages are singulated, they are ready to be electrically tested.
As described above, the electrical connecting patterns of the chip scale packages on the panel typically electrically interconnect with one another. This is one of the reasons the packages are singulated prior to their electrical testing. Because the chip scale packages are singulated prior to the individual electrical testing of each of the chip scale packages, the individual packages must be mounted or otherwise supported for testing. This is difficult because of the very small size of the packages and the desire to highly automate the testing process. Because of this difficulty in accurately supporting the singulated packages for testing, the packages cannot be easily tested in a reliable manner thereby slowing down and complicating the testing process. Also, because of the difficulty in handling the singulated packages for testing, the number of packages that fail the electrical testing process is potentially increased even though the packages may be good packages. These problems increase the overall cost of producing the chip scale packages. The present invention provides methods for producing and testing chip scale packages that eliminates the need to singulate the packages prior to testing thereby reducing the cost of producing and testing chip scale packages.
SUMMARY OF THE INVENTION
As will be described in more detail hereinafter, a methods for producing and electrically testing a chip scale integrated circuit package are herein disclosed. The methods include the step of providing a panel having a plurality of chip scale packages assembled on the panel. Each of the chip scale packages are electrically isolated from one another by cutting any electrically conductive paths which electrically interconnect the chip scale packages to one another on the panel. The step of electrically isolating the chip scale packages is done without singulating or physically separating the chip scale packages. The chip scale packages are then individually electrically tested while they remain physically connected to one another on the panel. After the chip scale packages are individually tested, the chip scale packages are singulated.
In one embodiment, the step of providing a panel having a plurality of chip scale packages includes the step of providing a substrate having a plurality of electrical connection patterns for electrically connecting an integrated circuit die to external electrical elements. The substrate has a top surface and a bottom surface. A plurality of integrated circuit die are attached to the top surface of the substrate. Each die is associated with a corresponding one of the electrical connection patterns. Bonding wires are formed to wire bond and electrically connect each of the die to their corresponding electrical connection patterns. The bonding wires and die are encapsulated by applying a layer of encapsulating material over the bonding wires, die, and top surface of the substrate thereby forming the panel including a plurality of chip scale packages.
In one version of the above described embodiment, the step of electrically isolating each of the chip scale packages includes the step of sawing grooves into the bottom surface of the substrate. The grooves extend substantially through the substrate but not through the layer of encapsulating material. This causes the chip scale packages to remain physically connected to one another by the layer of encapsulating material. The grooves also serve to cut any electrically conductive paths of the electrical connecting patterns which electrically interconnect the chip scale packages to one another on the panel.
Beyer Weaver & Thomas LLP
National Semiconductor Corporation
Niebling John F.
Zarneke David A
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