Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Patent
1998-03-30
2000-09-12
Whitehead, Jr., Carl
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
438116, H01L 21203
Patent
active
061177059
ABSTRACT:
A package for an integrated circuit is described, as are methods of making the package. The package includes a substrate having a generally planar first surface on which a metal die pad is formed. An integrated circuit die is attached to the metal die pad. An adhesive head surrounds the integrated circuit die and covers the exposed periphery of the metal die pad. A generally planar lid is in a press-fitted interconnection with the bead. An adhesive material covers conductive structures on the die, such as bonding pads, to prevent corrosion. Optionally, the package has vertical peripheral sides. The methods of making the package include methods for making packages individually, or making a plurality of packages simultaneously. Where a plurality of packages are made simultaneously, integrated circuit die are placed on each of a plurality of physically-joined package substrates on a generally planar sheet of substrate material. An adhesive bead is applied around each die. In cross-section, the bead has a central peak and a shorter peak on each side of the central peak. A sheet of lid material is placed onto the beads. After the bead is hardened, individual packages are formed by cutting the substrate sheet, lid sheet, and beads.
REFERENCES:
patent: 4159221 (1979-06-01), Schuessler
patent: 4530152 (1985-07-01), Roche et al.
patent: 4890383 (1990-01-01), Lumbard et al.
patent: 5001829 (1991-03-01), Schelhorn
patent: 5043004 (1991-08-01), Miyauchi
patent: 5102829 (1992-04-01), Cohn
patent: 5105260 (1992-04-01), Butera
patent: 5126818 (1992-06-01), Takami et al.
patent: 5192681 (1993-03-01), Chiu
patent: 5230759 (1993-07-01), Hirawa
patent: 5241133 (1993-08-01), Mullen, III et al.
patent: 5250470 (1993-10-01), Yamaguchi
patent: 5278429 (1994-01-01), Takenaka et al.
patent: 5336931 (1994-08-01), Juskey et al.
patent: 5414300 (1995-05-01), Tozawa et al.
patent: 5422615 (1995-06-01), Shibagaki et al.
patent: 5436203 (1995-07-01), Lin
patent: 5474957 (1995-12-01), Urushima
patent: 5578525 (1996-11-01), Mizukoshi
patent: 5593926 (1997-01-01), Fujihara
patent: 5641713 (1997-06-01), Kyle
patent: 5742007 (1998-04-01), Kornowski et al.
patent: 5801074 (1998-09-01), Kim et al.
Patent Abstracts of Japan, vol. 096, No. 012, Dec. 26, 1996, & JP 08 213498 A (Sumitomo Kinzoku Electro Device:KK), Aug. 20, 1996.
Patent Abstracts of Japan, vol. 011, No. 304 (E-545), Oct. 3, 1987, & JP 62 097355 A (Toshiba Corp), May 6, 1987.
Banerji, K., "Development of the Slightly Larger Than ICCarrier (SLICC)", Proceedings of the Feb. 27-Mar. 4, 1994, Technical Program NEPCON West '94, pp. 1249-1256.
Levine, B. and Guinther, F., "The Package", Electronic News, vol. 42, No. 2112 (1996), pp. 1, 32.
Glenn Thomas P.
Hollaway Roy D.
Panczak Anthony E.
Amkor Technology Inc.
Jr. Carl Whitehead
Parsons James E.
Potter Roy
LandOfFree
Method of making integrated circuit package having adhesive bead does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of making integrated circuit package having adhesive bead, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of making integrated circuit package having adhesive bead will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-95409