Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1996-11-06
1998-02-10
Chaudhari, Chandra
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438657, H01L 218242
Patent
active
057168830
ABSTRACT:
A method of creating an STC structure, used for high density, DRAM designs, has been developed. The process consists of creating a storage node electrode, for the STC structure, consisting of an upper polysilicon shape, comprised of polysilicon columns, with a narrow space between polysilicon columns, and an underlying lower polysilicon shape, residing in a contact hole, and making contact to underlying transistor regions. The polysilicon columns, and the narrow space, between polysilicon columns are formed via creation of a narrow trench in a top portion of a polysilicon layer, followed by an anisotropic etch to create the exterior shape of the storage node electrode. A key feature of this invention is the use of a photoresist plug, in the trench, used to protect the lower portion of the storage node electrode during the exterior shape, patterning process. This storage node electrode configuration results in increased surface area, via use of polysilicon columns, as well as density improvements, resulting from the use of narrow spaces between polysilicon columns.
REFERENCES:
patent: 5290729 (1994-03-01), Hayashide et al.
patent: 5447882 (1995-09-01), Kim
patent: 5468670 (1995-11-01), Ryou
patent: 5494841 (1996-02-01), Dennison et al.
Ackerman Stephen B.
Chaudhari Chandra
Saile George O.
Vanguard International Semiconductor Corporation
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