Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-01-04
2001-04-03
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S197000, C438S142000, C438S660000, C438S663000, C438S664000, C438S682000, C438S586000, C438S592000, C257S199000, C257S287000
Reexamination Certificate
active
06211000
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present invention relates generally to integrated circuit manufacture and more particularly to a method and structure in which a MOSFET is formed that has a gate polysilicon that has been converted into a silicide and which possesses enhanced conductivity.
2. Description of the Related Art
The structure and the various components, or features, of a metal oxide semiconductor (MOS) devices are generally well known. A MOS transistor typically includes a substrate material onto which a gate dielectric and a patterned gate conductor are formed. The gate conductor causes the impurities forwarded into the substrate on opposite sides of the gate conductor to self-align. The impurities placed into the substrate define a junction region, also known as source and drain regions. The gate conductor is patterned from a layer of polysilicon using various lithography techniques.
A typical n-channel MOS transistor employs N-type junctions placed into a P-type substrate. Conversely, a typical p-channel MOS transistor comprises P-type junctions placed into an N-type substrate. The substrate comprises an entire monolithic silicon wafer, of which, a portion of the substrate known as a “well” exists. The well is doped opposite the substrate so that it can accommodate junctions of an impurity type opposite the junction in the non well areas. Accordingly, wells are often employed when both N-type and P-type transistors (i.e., Complementary MOS, “CMOS”) are needed.
A common trend in modern integrated circuit manufacture is to produce transistors having feature sizes as small as possible. To form a high density integrated circuit, features such as the gate conductors, source and drain junctions, and interconnects to the junctions must be made as small as possible. Many modern day processes employ features which have as small as 0.20 microns critical dimensions. As feature sizes decrease, the size of the resulting transistors as well as the interconnections between transistors also decrease. Smaller transistor size allows more transistors to be placed on a single monolithic substrate, thereby allowing relatively large circuit systems to be incorporated on a single and relatively small die area. Further, smaller transistors typically have lower turn-on threshold voltages, faster switching speeds and consume less power in their operation. The combination of these features allow higher speed integrated circuits to be constructed. Additionally, these higher speed integrated circuits have greater processing capabilities and produce less heat.
The benefits of high-density integrated circuits can only be realized if advanced processing techniques are used. For example, semiconductor process engineers and researchers often study the benefits of electron beam lithography and x-ray lithography to achieve the higher resolutions needed for submicron features. To some extent, wet etch techniques are being replaced by more advanced anisotropic (dry etch) techniques. Further, silicides and polycides are replacing higher resistivity contact structures mostly due to the lower resistivity needed when a smaller contact area is encountered.
Many other techniques are often used to achieve a higher density circuit. However, these techniques must contend with problems resulting from higher density itself. Even the most advanced processing techniques cannot, in all instances, offset the problems associated with small features or features arranged extremely close to one another. For example, as the channel length decreases, short channel effects (“SCE”) generally occur. SCE cause threshold voltage skews at the channel edges as well as excessive subthreshold currents (e.g., punch through and drain-induced barrier lowering). Related to SCE is the problem of hot carrier injection (“HCI”). As the channel shortens and the supply voltage remains constant, the electric field across the drain-to-channel junction becomes excessive. Excessive electric fields give rise to so called hot carriers and the injection of these carriers into the gate oxide which resides between the substrate (or well) and the overlying gate conductor. Injection of hot carriers should be avoided since these carriers can become trapped and skew the turn-on threshold voltage of the ensuing transistor. In view of these considerations, certain scaling limits are being reached.
There also are additional problems that exist when attempting to reduce the channel length in scaled transistors. When the channel length of a transistor is reduced, the cross-sectional area of the gate conductor is also reduced. Because high speed operation of devices depends, in part, upon the conductivity of the gate conductor, the reduction in cross-sectional area of the gate conductor harms device performance. Thus, there exists a need in the art for a method of forming devices that have gate conductors with enhanced conductivity.
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by transistors formed according to the present invention that include a gate with enhanced conductivity as compared to prior devices. In forming a gate conductor according to the present invention, a gate polysilicon/silicidation metal gate structure is first formed upon a gate dielectric. In a rapid thermal process, the silicidation metal is reacted with the gate polysilicon to convert a substantial portion, or all of, the gate polysilicon to a silicide. When converted to the silicide, the gate conductor has increased bulk conductivity which causes the gate conductor to have improved performance for high-speed switching.
During the rapid thermal annealing steps that convert the gate polysilicon to a silicide, silicidation of the source and drain junctions may also be performed. By combining such steps, an efficiency in the manufacturing process is achieved. However, the amount of silicidation formed in the source and drain implants must be limited so that the source and drain implants are not consumed in the silicidation step. In contrast, it is advantageous to consume all of the polysilicon material in a gate conductor stack. Accordingly, the invention includes forming an aggressive consumption metal on top of the polysilicon gate conductor stack that will, in either one or two annealing steps, consume all or a significant portion of the gate conductor layer. On the other hand, because an aggressive consumption metal would consume too much of the source and drain implants, a second silicidation metal is formed on top of the source and drain implants as well as on top of the aggressive consumption metal that is on top of the gate conductor layer. The second consumption metal is one that is a far less aggressive consumption metal, and therefore does not tend to consume excessive amounts of the source and drain implant regions or of the device junctions.
These and other aspects of the present invention will become apparent with further reference to the drawings and specification which follow.
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Fulford Jr. H. Jim
Gardner Mark I.
Spikes Thomas E.
Advanced Micro Devices
Garlick Bruce E.
Harrison James A.
Lee, Jr. Grarril D.
Smith Matthew
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