Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-01-28
2001-05-08
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S591000, C438S592000, C438S664000
Reexamination Certificate
active
06228724
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present invention relates generally to integrated circuit manufacture; and more particularly to a method and structure in which a gate conductor is formed of a polysilicon material that has been converted to a silicide and in which a sandwiched gate insulator provides protection for a self-aligned channel region.
2. Description of the Related Art
The structure and the various components, or features, of a metal oxide semiconductor (MOS) device are generally well known. A MOS transistor typically includes a substrate material onto which a gate insulator and a patterned gate conductor are formed. The gate conductor serves to self-align impurities forwarded into the substrate on opposite sides of the gate conductor. The impurities placed into the substrate define a junction region, also known as source/drain regions. The gate conductor is patterned from a layer of polysilicon using various lithography techniques.
A typical n-channel MOS transistor employs n-type junctions placed into a p-type substrate. Conversely, a typical p-channel MOS transistor comprises p-type junctions placed into an n-type substrate. The substrate comprises an entire monolithic silicon wafer, in which, a portion of the substrate known as a “well” is formed. The well is doped opposite the substrate so that it can accommodate junctions of an impurity type opposite the junction in the non-well areas. Accordingly, wells are often employed when both n-type and p-type transistors (i.e. Complementary MOS, “CMOS”) are needed.
A pervasive trend in modern integrated circuit manufacture is to produce transistors having feature sizes as small as possible. To achieve a high density integrated circuit, features such as the gate conductor, source/drain junctions, and interconnects to the junction must be made as small as possible. Many modern day processes employ features which have less than 0.25 micron critical dimensions. As feature size decreases, the resulting transistor as well as the interconnect between transistors also decreases. Smaller transistors allow more transistors to be placed on a single monolithic substrate, thereby allowing relatively large circuit systems to be incorporated on a single and relatively small die area. Further, smaller transistors typically have lower turn-on threshold voltages, faster switching speeds and consume less power in their operation. These features in combination allow for higher speed integrated circuits to be constructed that have greater processing capabilities.
The benefits of high density circuits can only be realized if advanced processing techniques are used. For example, semiconductor process engineers and researchers often study the benefits of electron beam lithography and x-ray lithography to achieve the higher resolutions needed for submicron features. To some extent, wet etch has given way to a more advanced anisotropic (dry etch) technique. Further, silicides and polycides have replaced higher resistivity contact structures mostly due to the lower resistivity needed when a smaller contact area is encountered.
Many other techniques are often used to achieve a higher density circuit. However, these techniques must contend with problems resulting from higher density itself. Even the most advanced processing techniques cannot, in all instances, offset the problems associated with the use of small features or features arranged extremely close to one another. For example, as the channel length decreases, short channel effects (“SCE”) generally occur. SCE cause threshold voltage skews at the channel edges as well as excessive sub-threshold currents (e.g., punch through and drain-induced barrier lowering). Related to SCE is the problem of hot carrier injection (“HCI”). As the channel shortens and the supply voltage remains constant, the electric field across the drain-to-channel junction becomes excessive. Excessive electric fields give rise to so called hot carriers and the injection of these carriers into the gate oxide which resides between the substrate (or well) and the overlying gate conductor. Injection of hot carriers should be avoided since these carriers can become trapped and skew the turn-on threshold voltage of the ensuing transistor.
Another particular problem relating to the scaling of transistors is found in the formation of transistor gate dielectrics and gate conductors. In order to produce a scaled transistor, the gate dielectrics and gate conductors must be formed with less width and less thickness. Gate dielectrics are typically formed of silicon dioxide which is grown on the surface of active regions of the substrate. When transistors are scaled, the gate dielectric thickness must be reduced accordingly. However, when the silicon dioxide gate dielectric is less than approximately 10 Angstroms thick, it fails to function properly. Thus, a limitation exists in the use of silicon dioxide, or other similar materials as gate dielectrics in scaled transistors.
Further, the gate conductor must also be reduced in width to correspond to the reduced width of the gate dielectric. With its reduced dimensions, the resistance of the gate conductor increases. Thus, the gate conductor is typically heavily doped to increase its conductivity so that the transistor will function properly. However, the dopant in the gate conductor tends to migrate into and through the gate dielectric, thereby depleting the dopant near the gate dielectric. This migration of dopant is referred to as the “polysilicon depletion effect” and results in altered turn-on threshold voltages and poor transistor performance.
Thus, there exists a need in the art for an improved gate conductor/gate dielectric structure that will minimize the problems resulting from transistor scaling.
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by transistors and an integrated circuit formed according to the present invention. In forming such transistors, active regions and isolation regions are formed in a substrate. Wells may also be formed so that differing types of transistors may be formed in a single substrate. With the active regions and isolation regions formed, an oxide layer is formed to a thickness of between 15 and 25 Angstroms across the substrate and partially removed so that a thickness of approximately 4 Angstroms remains. Then a nitride layer is formed upon oxide layer to a thickness of 10 to 20 Angstroms. Polysilicon gate conductors are then formed above the active regions of the substrate using a deposition and patterning technique.
Spacers are then formed about the polysilicon gate conductor, lightly doped drain regions are formed and then source/drain regions are formed. In forming the lightly doped drain regions and the source/drain regions, the polysilicon gate conductor is doped. Then, a silicidation metal layer is deposited upon the polysilicon gate conductors and exposed portions of the nitride layer. The resultant structure is then subjected to an annealing step in which the polysilicon gate conductor is converted to a silicide gate conductor having a relatively lower bulk resistance.
With the conversion complete, the remaining portions of the silicide metal layer are removed. Openings are then made to the source/drain regions through which interconnections are made to the transistor. A plurality of transistors formed according to this technique may be interconnected to form an integrated circuit.
Silicidation of the source/drain regions may be accomplished using differing techniques according to the present invention. Using a first technique, silicidation of the source/drain regions is performed after portions of the oxide layer and nitride layer residing upon the source/drain regions have been removed. Alternately, an aggressive silicidation metal, e.g., titanium, may be employed which will form silicidation of the source/drain regions during conversion of the polysilicon gate conductor to the silicide gate conductor.
By forming the oxide layer
itride layer gate insulator, dopant migration from the polysilicon
Fulford Jr. H. Jim
Gardner Mark I.
Spikes Thomas E.
Advanced Mirco Devices
Chaudhari Chandra
Garlick Bruce
Harrison James
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