Method of making gate dielectric for sub-half micron MOS transis

Details Method of making gate dielectric for sub-half micron MOS transis Method of making gate dielectric for sub-half micron MOS transis

1997-10-29

2000-01-18

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438591, 438785, H01L 21336

Patent

active

060157399

ABSTRACT:
A process for fabricating a gate dielectric stack of a MOS transistor. A native oxide film is formed on an upper surface of a semiconductor substrate. A silicon nitride layer is then deposited on the native oxide film. A final dielectric film is then formed on the silicon nitride film. A dielectric constant of the final dielectric film is in the range of approximately 20-200. The substrate is then annealed in an inert ambient to produce the gate dielectric stack. An equivalent silicon dioxide thickness of the dielectric stack is typically in the range of approximately 5-20 angstroms whereby a gate dielectric stack suitable for use in deep sub-micron transistor is fabricated with a film thickness substantially in excess of an electrically equivalent silicon dioxide film. A suitable material for the final dielectric film includes oxides comprising oxygen and an element such as beryllium, magnesium, calcium, zirconium, titanium, or tantalum.

REFERENCES:
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patent: 5464792 (1995-11-01), Tseng et al.
patent: 5834353 (1998-11-01), Wu
Ghandhi, S.K., "VLSI Fabrication Principles, Silicon and Gallium Arsenide", pp. 372-373, 427-430, 1983.

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