Method of making field effect transistors having...

Details Method of making field effect transistors having... Method of making field effect transistors having...

2006-06-27

2006-06-27

Lindsay, Jr., Walter L. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S230000, C438S303000

Reexamination Certificate

active

07067366

ABSTRACT:
A method is provided for defining spacings between the gates of field effect transistors (FETs) of an integrated circuit and the source and drain regions thereof, the spacings differing in width between a first FET and a second FET. The method includes forming gate stacks of the integrated circuit over a substrate, and forming first spacers on sidewalls of the gate stacks. Second spacers are then formed over the first spacers. Thereafter, source and drain regions of the first FET are formed in alignment with the second spacers of a first gate stack of the gate stacks. The second spacers are then removed from the first spacers of the gate stacks. Thereafter, the first spacers of a second gate stack are anisotropically etched in a substantially vertical direction to remove horizontally extending portions of the first spacers, and source and drain regions of the second FET are formed in alignment with portions of the first spacers of the first gate stack which remain after the etching.

REFERENCES:
patent: 6316302 (2001-11-01), Cheek et al.
patent: 6855988 (2005-02-01), Madurawe
patent: 6908822 (2005-06-01), Rendon et al.
patent: 2002/0197806 (2002-12-01), Furukawa et al.

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