Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-06-19
2003-09-23
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S305000, C438S366000, C438S231000
Reexamination Certificate
active
06624034
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device of MIS (metal insulator semiconductor) type using a :field effect and a production method thereof. More specifically, it relates to a semiconductor device in which the increase of parasitic capacitance is restrained while restraining punch-through and other effects generated by scale reduction, and a production method thereof.
2. Description of the Background Art
In order to provide a CMOS (complementary metal oxide semiconductor) having a higher performance, improvement of intrinsic performance by scale reduction is needed. Disadvantages accompanying the scale reduction include punch-through, the short channel effect, and other effects. In order to restrain punch-through and the short channel effect, a method is proposed in which the source/drain regions of first conductivity type are covered with a second conductivity type impurity region so that the source/drain regions may not directly face the channel region (Y. Okumura et. al., IEEE Trans. Electron Devices, vol. 39, No. 11, p. 9541 (1992)).
Referring to
FIG. 28
, in the semiconductor device disclosed in the aforesaid document by Okumura et al., a channel region
106
is disposed in a p-well
102
in a p-type silicon substrate
101
. An extension region
105
extending from the source/drain regions
104
is covered with a p-type impurity region
103
so that the extension region
105
may not directly face the channel region
106
. In the following descriptions, the p-type impurity region
103
will be referred to as a pocket injection region; however, in the aforesaid document, the p-type impurity region
103
is referred to as NUDC (non-uniformly doped channel) layer. A gate electrode
108
is formed on the channel region
106
with an intervening gate dielectric film
107
.
If the above-mentioned pocket injection region
103
is not present, a junction is formed between the source/drain regions
104
of the n-type impurity region and the p-type well
102
,
50
that when a reverse bias voltage is applied, a depletion layer extends to the p-well side, having a low impurity concentration. In other words, as the reverse bias voltage increases, the depletion layer extends towards the aforesaid channel region
106
and, depending on the degree of scale reduction of the channel length, punch-through occurs easily. If the p-type impurity concentration of the pocket injection region
103
is increased, the extension of the depletion layer towards the pocket injection region side is restrained. Therefore, by increasing the p-type impurity concentration of the pocket injection region
103
, the extension of the depletion layer, which is generated in the junction formed between the source/drain regions
104
of the n-type impurity region and the p-type well
102
, to the channel region
106
side can be prevented. This restrain t of the extension of the depletion layer acts effectively as a restraint of punch-through and a restraint of the short channel effect. As a result of this, scale reduction of semiconductor devices such as CMOS can be achieved without raising problems such as punch-through.
However, as shown in
FIG. 28
, the pocket injection region into which an impurity has been injected, i.e., ion implanted, is in contact with a bottom surface
109
of the source/drain regions over a wide range. A junction capacitance is generated at the junction of the p-type pocket injection region and the n-type source/drain regions. This junction capacitance is proportional to the area of the junction and increases as the junction becomes wider. Further, if the p-type impurity concentration of the pocket injection region is increased, the junction capacitance increases due to the decrease in the width of the depletion layer and due to the impurity concentration itself. If the junction capacitance increases, the operational characteristics of the semiconductor device deteriorate and the switching speed decreases. For this reason, there are cases in which the impurity concentration of the pocket injection region cannot be increased to a suitable level in an attempt to restrain punch-through and other effects. Scale reduction of the semiconductor devices is a perpetual goal to be achieved, and there is a need to solve these obstacles to scale reduction.
SUMMARY OF THE INVENTION
Thus, an object of the present invention is to provide a semiconductor device that makes it possible to restrain the increase of the junction capacitance and others while preventing the punch-through and others accompanying the scale reduction, and a production method thereof.
A semiconductor device of the present invention includes source and drain regions of first conductivity type disposed to sandwich a channel region located in a surface part of a semiconductor layer, and a pair of pocket injection regions of second conductivity type that cover only a neighborhood of respective side surface parts of the source and drain regions on the channel region side and form a junction only between the neighborhood of the side surface parts and the pocket injection regions.
In the above construction, the pocket injection regions and the source/drain regions form a junction at the aforesaid side surface to be in an electrically conducted state, and the pocket injection regions having a raised impurity concentration of second conductivity type restrain the extension of the depletion layer from the aforesaid junction to the pocket injection regions. For this reason, the punch-through, the short channel effect, and others accompanying the scale reduction of semiconductor devices can be restrained. Further, as described above, since the junction is limited to the side surface of the source/drain regions, the area of the junction will be extremely small as compared with the conventional semiconductor devices. Therefore, the increase of the junction capacitance, which increases in proportion to the area of the junction, is restrained, thereby preventing the deterioration of the operation characteristics and the decrease of the switching speed of the semiconductor device. As a result of this, the increase of the junction capacitance parasitic to the junction between the pocket injection regions and the source/drain regions can be restrained while preventing the punch-through, the short channel effect, and others accompanying the scale reduction of semiconductor devices.
In the aforesaid semiconductor device of the present invention, the source and drain regions include source extension and drain extension regions of first conductivity type that extend towards the channel region, and each of the pocket injection regions covers a side surface and a bottom surface of the source extension and drain extension regions on the channel region side to form a junction.
If the extension regions are formed in the source/drain regions, the pocket injection regions cover, from the lower side, the whole of the extension regions from the channel region side to the bottom surface to form a junction so that the surface of the extension regions may not be exposed to the channel region. Therefore, the extension of the depletion layer to the pocket injection region can be prevented by increasing the second conductivity type impurity concentration in the pocket injection regions. Since the extension regions are formed in an extremely limited range as compared with the source/drain regions, the area of the junction does not increase even if the whole of the extension regions that are exposed to the channel region is covered. Therefore, the increase of the junction capacitance is restrained, thereby preventing the deterioration of the operation characteristics and the decrease of the switching speed of the semiconductor device. Therefore, the increase of the junction capacitance can be restrained while preventing the disadvantages such as the punch-through accompanying the scale reduction of semiconductor devices. Here, if the whole of the side surface of the aforesaid source/drain regions is
Abe Yuji
Miura Naruhisa
Oishi Toshiyuki
Sugihara Kohei
Tokuda Yasunori
Leydig , Voit & Mayer, Ltd.
Mitsubishi Denki & Kabushiki Kaisha
Nelms David
Tran Long
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