Method of making elevated source/drain using poly underlayer

Details Method of making elevated source/drain using poly underlayer Method of making elevated source/drain using poly underlayer

1998-08-26

2001-04-03

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

Reexamination Certificate

active

06211025

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly, to an integrated circuit transistor with elevated source/drain regions, and to a method of making the same.
2. Description of the Related Art
A typical field effect transistor implemented in silicon consists of a source and a drain formed in a silicon substrate, and separated laterally to define a channel region in the substrate. A gate electrode composed of a conducting material, such as aluminum or polysilicon, is disposed over the channel region and designed to emit an electric field into the channel region. Changes in the electric field emitted by the gate electrode enable, or alternatively, disable the flow of current between the source and the drain.
In a conventional process flow for forming a typical field effect transistor, a gate oxide layer is grown on a lightly doped silicon substrate and a layer of polysilicon is deposited on the gate oxide layer. The polysilicon and the gate oxide are then anisotropically etched back to the upper surface of the substrate leaving a polysilicon gate electrode stacked on top of a gate oxide layer. Following formation of the polysilicon gate electrode, a source and a drain are formed by implanting a dopant species into the substrate. The gate electrode acts as a hard mask against the implant so that the source and drain are formed in the substrate self-aligned to the gate electrode. Many conventional semiconductor fabrication processes employ a double implant process to form the source and drain. The first implant is performed self-aligned to the gate electrode to establish lightly doped drain (“LDD”) structures. After the LDD implant, dielectric sidewall spacers are formed adjacent to the gate electrode by depositing and anisotropically etching a dielectric material, such as silicon dioxide. The second of the two source/drain implants is then performed self-aligned to the sidewall spacers. The substrate is then annealed to activate the dopant in the source and the drain. Salicidation steps frequently follow the formation of the source and drain.
Early MOS integrated circuits were implemented as p-channel enhancement mode devices using aluminum as the gate electrode material. Aluminum had the advantages of relatively low resistivity and material cost. Furthermore, there was already a large body of manufacturing experience with aluminum in the chip industry developed from bipolar integrated circuit processing.
A later process innovation that is still widely used today, involves the use of heavily doped polysilicon as a gate electrode material in place of aluminum. The switch to polysilicon as a gate electrode material was the result of certain disadvantages associated with aluminum in early fabrication technologies. In conventional semiconductor fabrication processing, aluminum must be deposited following completion of all high temperature process steps (including drive-in of the source and drain regions). As a result, an aluminum gate electrode must ordinarily be separately aligned to the source and drain. This alignment procedure can adversely affect both packing density and parasitic overlap capacitances between the gate and source/drain regions. In contrast, polysilicon with its much higher melting point, can be deposited prior to source and drain formation and therefore provide for self-aligned gate processing. Furthermore, the high temperature capability of polysilicon is routinely exploited to enable interlevel dielectric layers to be applied to provide multiple metallization layers with improved planarity.
Despite the several advantages of polysilicon over aluminum as a gate electrode material, polysilicon has the disadvantage of a much higher resistivity as compared to aluminum. Higher resistivity translates into higher values of interconnect line resistance that can lead to undesirably long RC time constants and DC voltage variations within VLSI or ULSI circuits. The development of polycide films on top of polysilicon layers has alleviated some of the resistivity shortcomings of polysilicon gate electrodes. However, the resistivity of polysilicon gate electrodes in conventional MOS integrated circuit processing still presents a potential impediment to successful process scaling through reductions in the operating voltages of VLSI and ULSI devices.
Another disadvantage of polysilicon as a gate electrode material is polysilicon depletion. In p-channel transistors, the source and drain are commonly formed in the substrate by implanting a p-type dopant, such as boron. The implant also deposits boron into the polysilicon of the gate electrode. Subsequent thermal processing steps to fabricate a conventional p-channel field effect transistor frequently cause boron to diffuse from the gate electrode through the gate oxide layer and into the channel region. If the amount of boron diffused is sufficiently high, the electrical performance of the field effect transistor may be severely degraded due to polysilicon depletion.
Conventional source/drain region processing also presents certain disadvantages. Typically, the source and a drain are formed on opposite sides of the gate electrode by implanting dopant atoms directly into the silicon substrate. The lateral spacing between the source and the drain defines a channel region for the transistor. In conjunction with several other factors, the width of the channel region or “channel length” determines the ultimate speed of the transistor. As a general rule of thumb, smaller channel widths translate into both higher switching speeds and smaller die areas. As advances in process technologies have reduced the minimum feature size to the 0.2 &mgr;m level and below, channel lengths have plummeted. However, realization of the performance benefits associated with short channel lengths requires source/drain regions with rather shallow junctions, that is, junctions positioned near the upper surface of the substrate. Shallow positioning of source/drain junctions can be hard to achieve. The difficulty stems in part from the propensity of some of the dopant atoms in virtually any implant to tunnel or penetrate deeply into the substrate, particularly where there is no intervening structure between the impinging dopant atoms and the upper surface of the substrate. Later heating steps also tend to drive the junctions deeper, particularly for small diameter dopant atoms, such as boron. Off-axis implantation can reduce but not eliminate the potential for tunneling.
Aside from the drawbacks associated with conventional gate electrode and source/drain manufacture, the dielectric sidewall spacer formation aspects of conventional transistor fabrication present certain disadvantages. Although frequently composed of the same material, namely, silicon dioxide, conventional gate dielectric layers and sidewall spacers are commonly formed in completely separate oxidation or chemical vapor deposition steps that require two separate masking and high temperature heating steps. The number of required masking steps is primarily an economic issue tied to the longer through-put time required for the process flow. However, the additional heating step can adversely affect the properties of the source/drain regions. In many conventional process flows, spacer formation follows not only the LDD implant but also the second, and heavier doping source/drain region implant. The heating associated with spacer formation can alone, or in concert with later heating steps, drive the junctions of the source/drain regions to undesirable depths, and/or exacerbate polysilicon depletion in the case of p-channel devices.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.
SUMMARY OF THE INVENTION
In accordance with one aspect of the present invention, a method of fabricating a transistor on a substrate is provided. The method includes the steps of forming a semiconductor layer on the substrate and a via in the semiconductor layer extendin

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