Method of making dynamic memory device with increased charge...

Details Method of making dynamic memory device with increased charge... Method of making dynamic memory device with increased charge...

2000-08-03

2001-10-16

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S253000

Reexamination Certificate

active

06303428

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device such as a dynamic memory and a method of manufacturing the same.
2. Related Art of the Invention
It has conventionally been known that a leakage current generated in a memory cell of a dynamic memory adversely affects the charge retention characteristic of the memory cell. To prevent this, for example, in a semiconductor device disclosed in Japanese Laid-open Patent Application No. S62-2562, both of the source and drain diffusion regions are formed low in concentration in a transistor which is a portion of a memory cell where the leakage current is necessarily prevented. FIG.
4
(
a
) shows the structure thereof. In the figure, reference numeral
41
represents a silicon substrate (first conductivity type), reference numeral
42
represents an isolation oxide film (LOCOS), reference numeral
43
represents a gate oxide film, reference numeral
44
represents a gate electrode, reference numeral
45
represents low-concentration source and drain diffusion regions (second conductivity type), reference numeral
46
represents an oxide film, reference numeral
47
represents high-concentration source and drain diffusion regions (second conductivity type), and reference numeral
48
represents a lower electrode of a cell capacitor. The low-concentration source and drain diffusion regions
45
correspond to the both of the surface and drain diffusion regions of a transistor which is a portion where the leakage current is necessarily prevented.
Examples of means for increasing the capacity of the cell include one as disclosed in Japanese Laid-open Patent Application No. H2-177359. FIG.
4
(
b
) shows the structure thereof. Portions the same as those shown in FIG.
4
(
a
) will be described by use of the same reference numerals. Reference numeral
41
represents a silicon substrate (first conductivity type). Reference numeral
42
represents an isolation oxide film (LOCOS). Reference numeral
43
represents a gate oxide film. Reference numeral
44
represents a gate electrode. Reference numeral
45
represents low-concentration source and drain diffusion regions (second conductivity type). Reference numeral
46
represents an oxide film. Reference numeral
48
represents a lower electrode of a cell capacitor. Reference numeral
49
represents a high-concentration diffusion region (first conductivity type). In one of the diffusion regions (the one connected to the cell capacitor) in the source and the drain, the high-concentration diffusion region
49
having the same conductivity type as the substrate is formed and the capacity of the cell is increased by use of the junction capacitance.
However, since devices has recently become denser as the degree of integration increases, it is necessary to decrease the depth of the diffusion regions in order to prevent a short channel effect of a switching transistor. Therefore, only reducing the concentration of both of the source and drain diffusion regions like in the prior arts degrades the junction characteristic because the surface of the semiconductor substrate is etched in forming the contact hole for connecting the diffusion layers and the cell capacitor, so that the leakage current increases.
Moreover, forming the high-concentration diffusion regions of the different conductivity type so as to adjoin the drain and source diffusion regions in order to increase the capacity of the cell also increases the leakage drain.
Thus, the conventional methods all present a problem that the charge retention characteristic is degraded.
SUMMARY OF THE INVENTION
The present invention solves the above-mentioned conventional problems and an object thereof is to provide a semiconductor device and a method of manufacturing the same wherein a necessary charge retention characteristic is satisfied, there is little variation with time and long-term reliability is high.
The present invention is a semiconductor device comprising:
a gate electrode (
4
) formed of a conductive material on a semiconductor substrate (
1
) of one conductivity type with a gate insulating film (
3
) therebetween;
first and second diffusion regions (
5
,
10
) of another conductivity type formed on said semiconductor substrate (
1
) so as to sandwich said gate electrode (
4
); and
a contact hole (
17
) for electrically connecting one (first) (
10
) of said first and second diffusion regions (
5
,
10
) to a lower electrode (
8
) of a cell capacitor for storing charge therein,
wherein said semiconductor device has a characteristic that when a reverse voltage Vrev is applied as a junction application voltage between semiconductors of different conductivity types of said first diffusion region (
10
) and said semiconductor substrate (
1
) (positive potential is applied to the n-type semiconductor side and zero or negative potential, to the p-type semiconductor side), a leakage current Ileak flows between said first diffusion region (
10
) and said semiconductor substrate (
1
), and said junction application voltage Vrev when the leakage current Ileak is
Ileak=Cs×(Vbit/2)×(1/T)×(1/S)
(where a charge storage capacitance in said cell capacitor is Cs, a voltage applied to a data line (
12
) connected to the other (second) (
5
) of said first and second diffusion regions (
5
,
10
) is Vbit, a target charge retention time is T and an area of the first diffusion region (
10
) is S) is three times or higher than the voltage Vbit applied to said data line (
12
) at room temperature.


REFERENCES:
patent: 4417325 (1983-11-01), Harari
patent: 4977099 (1990-12-01), Kotaki
patent: 5440165 (1995-08-01), Mitsunaga et al.
patent: 5932906 (1999-08-01), Shimizu
patent: 62-2562 (1987-01-01), None
patent: 2-177359 (1990-07-01), None
patent: 5-259385 (1993-10-01), None

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