Method of making dual-gate CMOSFET

Details Method of making dual-gate CMOSFET Method of making dual-gate CMOSFET

1998-03-02

2000-01-04

Niebling, John F.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438199, 438299, 438301, H01L 21336

Patent

active

060109254

ABSTRACT:
A method of making dual-gate structure with only three masking steps is provided. The process comprising: forming well and isolation region to define PMOS and NMOS regions on a semiconductor substrate; forming a conformal layer of PMOS gate oxide by thermal oxidation; providing a conformal layer of P type conducting material overall; removing portions of the P type material and PMOS gate oxide on the NMOS region with the aid of the first patterned mask; forming a conformal layer of NMOS gate oxide by thermal oxidation; providing a conformal layer of N type conducting material overall; forming the NMOS gate structure with the aid of the second patterned mask; performing ion implantation; providing a conformal layer of oxide overall, then etching into NMOS spacers; performing ion implantation; providing a conformal layer of protecting dielectric layer overall; proving the third patterned mask to remove portions of the protecting dielectric layer, the NMOS gate oxide, P type conducting layer and PMOS gate oxide to form the PMOS gate structure, thereby leaving a protecting dielectric layer over the NMOS region; performing ion implantation; providing a conformal layer of oxide overall, then etching into PMOS spacers; performing ion implantation.

REFERENCES:
patent: 5849616 (1998-12-01), Ogoh

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