Method of making contactless nonvolatile semiconductor memory wi

Details Method of making contactless nonvolatile semiconductor memory wi Method of making contactless nonvolatile semiconductor memory wi

1998-05-15

2000-03-14

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438286, 438657, H01L 218247

Patent

active

060372265

ABSTRACT:
A contactless, nonvolatile metal oxide semiconductor memory device having a rectangular array of memory cells interconnected by word-lines in the row direction of the array and bit-lines in the column direction of the array. Each memory cell has a structurally asymmetrical pair of floating gate, MOS field effect transistors of the same row that share a common source region (bit line) within a semiconductor substrate. The asymmetry of the structure of the floating gates of the two transistors enables programming/reading and monitoring of the cell to be effected simultanetdsly. The structure of the floating gate is also responsible for a relatively large capacitive coupling between the floating gates and the control gate (word line) which lies above them. Since the floating gates essentially serve as a mask for implantation of program/read and monitor drain regions within the substrate, fabrication of the device incorporates self-aligning process steps.

REFERENCES:
patent: 5010028 (1991-04-01), Gill et al.
patent: 5047362 (1991-09-01), Bergemont
patent: 5352619 (1994-10-01), Hong
patent: 5763309 (1998-06-01), Chang
Kume, et al, "A 1.28.mu.m.sup.2 Contactless Memory Cell Technology for a 3V-Only 64Mbit EEPROM,"IEDM 92,p. p.92-991 to 92-993.

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