Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-03-27
2001-08-14
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S589000, C438S263000
Reexamination Certificate
active
06274432
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a contactless nonvolatile semiconductor memory device.
2. Description of the Related Art
In a nonvolatile semiconductor memory device such as a flash electrically-erasable programmable read-only memory (EEPROM) or an electrically programmable read-only memory (EPROM), the integration has been advanced by constructing bit lines as buried impurity diffusion layers.
In a prior art contactless nonvolatile semiconductor memory device, buried impurity diffusion layers as bit lines are formed beneath thick insulating layers (see J. Esquivel et al., “High Density Contactless, Self-aligned EPROM Cell Array Technology”, IEDM Technical Digest, pp. 592-595, 1986). This will be explained later in detail.
In the above-mentioned prior art contactless nonvolatile semiconductor memory device, however, when the integration is advanced so that a spacing between the buried impurity diffusion layers becomes narrow, leakage currents flowing therebetween are increased, which invites a malfunction of nonvolatile memory cells. Also, this creates a serious short channel effect.
In addition, when patterning floating gate electrodes by a dry etching process, the buried impurity diffusion layers are also etched. As a result, the resistance of the buried impurity diffusion layers is increased, which reduces the read operation speed of the device.
SUMMARY OF THE INVENTION
It is an object of the present invention to reduce the leakage currents between buried impurity diffusion layers serving as bits lines in a contactless semiconductor memory device.
Another object of the present invention is to suppress the short channel effect of memory cells.
A further object of the present invention is to avoid the etching of the buried impurity diffusion layers.
According to the present invention, in a contactless nonvolatile semiconductor memory device including a semiconductor substrate and a plurality of impurity diffusion layers serving as sub bit lines of a rectangular shape on the semiconductor substrate, a plurality of grooves of a rectangular shape are formed in the semiconductor substrate between the impurity diffusion layers. Also, a first gate insulating layer is formed on the semiconductor substrate within the grooves, and a plurality of floating gate electrodes are formed on the first gate insulating layer. Further, a second gate insulating layer is formed on the floating gate electrodes, and a plurality of word lines are formed on the second gate insulating layer. Thus, the distance between the buried impurity diffusion layers is increased by the presence of the grooves, which reduces leakage currents therebetween.
Also, a plurality of insulating layers are formed on the buried impurity diffusion layers. Thus, when patterning floating gate electrodes, the buried impurity diffusion layers are hardly etched due to the presence of the insulating layers thereon.
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J. Esquivel et al., “High density contactless, self aligned EPROM cell array technology”, pp. 592-595, IEDM Technical Digest, 1986.
Chaudhari Chandra
NEC Corporation
Yougn & Thompson
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