Method of making an integrated circuit using an EUV mask...

Details Method of making an integrated circuit using an EUV mask... Method of making an integrated circuit using an EUV mask...

2002-08-16

2004-12-28

Cuneo, Kamand (Department: 2829)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Multiple layers

C438S493000

Reexamination Certificate

active

06835671

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to methods for making integrated circuits and more particularly to methods for making integrated circuits using EUV lithography and reflective masks.
BACKGROUND OF THE INVENTION
In making integrated circuits it is desirable to improve the lithography by using shorter and shorter wavelengths for exposing photoresist on semiconductor wafers. These shorter wavelengths allow for higher resolution and require special masks for achieving that higher resolution. One of the techniques that is being developed for high volume manufacturing is using extreme ultraviolet (EUV) frequencies, which have very short wavelengths. Wavelengths from 4 to 25 nanometers (nm) are considered EUV. This technology generally requires a reflective mask, as distinct from a transmission mask, because materials useful as mask materials tend to have high absorption at EUV wavelengths. EUV light is reflected off of the mask and exposes the photoresist according to the pattern of mask. In making the mask, there is first an EUV blank having multi-layer stack on a substrate. The multi-layer stack is reflective. An absorber portion is formed and patterned over the reflective portion to leave a reflective pattern underneath. The reflective pattern is what is actually exposed on the photoresist. In making these masks, the features that are ultimately reflected onto the integrated circuit are extremely fine features. Accordingly, the mask must be extremely high quality and only provide the desired pattern.
One of the difficulties has been having a multi-layer stack in the blank that provides a high degree of reflection at the desired frequency. One of the difficulties has been that the individual layers that make up the multi-layer stack are not of the correct thickness with the result that the frequency that is reflected is not be the desired frequency. The result is a reduction in the amount of light energy that reaches the portions of photoresist on the wafer that are to be exposed. Reduced energy for exposure lower the exposure throughput. Another difficulty is that the layers are not of sufficiently uniform thickness resulting in different frequencies being reflected at different spatial locations on the mask. Non-uniform exposure of the wafer pattern results in non-uniform pattern fidelity or linewidth. This non-uniform pattern fidelity results in integrated circuits having low performance or that are defective.
Accordingly, there is a need for a mask blank that has a multi-layer stack with more accuracy and more uniform thickness.


REFERENCES:
patent: 6200893 (2001-03-01), Sneh
patent: 6248640 (2001-06-01), Nam
patent: 6284646 (2001-09-01), Leem
patent: 6287965 (2001-09-01), Kang et al.
patent: 6392792 (2002-05-01), Naulleau
patent: 6396900 (2002-05-01), Barbee et al.
patent: 2002/0028556 (2002-03-01), Marsh et al.
George, “Atomic Layer Deposition of A12O3/ZnO Nanolaminates & Alloys,” Presented Dec. 20, 2001 at Lawrence Livermore National Laboratory in Livermore, CA., 35 pgs.

Affiliated with

Also associated with

Rating

Method of making an integrated circuit using an EUV mask... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of making an integrated circuit using an EUV mask..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of making an integrated circuit using an EUV mask... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3302483