Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-06-23
2001-04-24
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
Reexamination Certificate
active
06221720
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method of fabricating an electronic device suitable for single-electron devices, various quantum effect devices and the like as well as to the electronic device fabricated by such a method.
In order to improve the performance of the electronic device, such as a silicon integrated circuit (LSI), fine-structuring of elements constituting the circuit is being advanced. However, MOS transistors mainly used at present in the devices have a limitation in improving integration and operation speed by this fine-structuring while suppressing increased power consumption.
Recently, in order to solve the limitation, single-electron elements have been proposed as electronic elements based on a new operation principle. When the elements are realized ideally, it is expected that the power delay product can be improved greatly. The single-electron element is described in, for example, APPLIED PHYSICS, Vol. 63, No. 12 (1994), pp. 1232-1238. Further, it is considered that the 0-dimensional quantum box for confining electrons in an area of several nm three-dimensionally can be used to improve the performance of light emitting elements or the like greatly by the quantum effect. In addition, it is considered that a one-dimensional quantum line can be used to form one-dimensional electron gas, so that the mobility of electrons can be increased greatly and a high-speed switching element can be realized. The 0-dimensional quantum box ideally means that electrons are fixed at one point of coordinates and the one-dimensional quantum line ideally means that electrons can be moved only in one direction. The quantum effect elements are discussed in, for example, the report of the Institute of Electronics and Communication Engineers of Japan, Vol. 77, No. 11 (1994), pp. 1117-1124.
However, as discussed in the above paper, in order to operate the single-electron device at room temperature, it is necessary to fabricate a device structure having a size of several nm which is smaller by one or two orders than several hundred nm for the size of the currently leading MOS transistor with accuracy. The quantum effect element such as the 0-dimensional quantum box and the one-dimensional quantum line are also the same.
For example, it is considered that an electron storage node is connected through two tunnel junctions to an external wiring. When a voltage is applied from the external wiring, electrons attempt to pass through the electron storage node through the tunnel junctions. However, energy of the electron storage node is increased by the storage energy for one electron in a short time that the electron passes through the electron storage node and consequently a next electron is prevented from entering the storage node subsequently. Thus, for example, by disposing a gate electrode to change a potential of the electron storage node by application of a voltage from the gate, a tunnel current passing through the storage node can be controlled. However, in order to attain such control at the room temperature, the energy in case where one electron is stored in the storage node must be sufficiently larger than thermal noise.
In other words, e
2
/2C>kT and accordingly the following equation must be satisfied.
C
(
aF
)<929
/T
(
K
)
where e represents an elementary charge, C represents a capacitance of the electron storage node, T represents an operating temperature in Kelvin, k represents the Boltzmann's constant, and a of aF represents an abbreviation of “atto-” meaning 10
−18
. When a sectional area, a thickness and a dielectric constant of the two tunnel junctions are S, d and e, respectively, the following equation is given using C=2&egr;S/d
S<e
2
d
/4
&egr;kT
For example, when the thickness of tunnel insulative layer is 2 nm, the sectional area S of the tunnel junctions is required to be made sufficiently smaller than 200 nm
2
in order to satisfy the above condition at the room temperature. That is, it is necessary to form tunnel junctions having a sectional area of at least 100 nm
2
or less, preferably several nm
2
to several tens nm
2
.
At present, there is no fabricating apparatus capable of attaining such super-fine structures and furthermore there is scarcely any prospect capable of attaining mass production with good reproductivity. Further, in order to achieve stable operations for the single electron devices, it is desirable to form a multi-tunnel junction having tunnel junctions formed in series, while a more complicated fabricating process is required therefor and it is difficult to cope with the process by the current lithography technique.
Furthermore, an experimental result that thin layers are laminated on a substrate to form tunnel junctions is reported in Journal of Non-Crystalline Solids, 128 (1991), 91-100. However, there is no teaching as to how transistors, memories and light emitting elements are fabricated when the laminated structure is formed on the substrate in the vertical direction to the substrate to form the tunnel junctions. A relevant memory technique is disclosed in U.S. Ser. No. 291,752 filed Aug. 16, 1994 and assigned to the same assignee as the present invention (U.S. Pat. No. 5,600,163).
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a fabricating method of an electronic device in which a semiconductor pattern formation apparatus and a device fabricating apparatus used in conventional fabrication of a silicon integrated circuit can be used to accurately attain the dimension of several nm required to operate single-electron elements and various quantum effect elements at room temperature and an electronic device having an element structure fabricated by this method.
In order to achieve the above object, according to the present invention, laminated layers including semiconductor or metal thin layers and insulative thin layers are formed on a substrate and after the laminated layers are patterned, and the laminated layers are oxidized from their side to form an oxidized area, so that a 0-dimensional quantum box or one-dimensional quantum line having fine tunnel junctions surrounded by the oxidized area and a 0-dimension quantum box or one-dimensional quantum line made of semiconductor or metal area interposed between the oxidized area and the insulative thin layers are formed in the laminated layers.
When the laminated layers processed into the form of pillar are oxidized, the semiconductor or metal line including fine tunnel junctions or 0-dimensional quantum box on the way of the pillar in the center of the pillar and extending in the substantially perpendicular direction to the substrate are obtained.
Alternatively, laminated layers in which semiconductor or metal thin layers are interposed between a plurality of insulative layers are processed into an oblong rectangular parallelepiped and when the rectangular parallelepiped is oxidized from its side, semiconductor or metal lines extending in the substantially parallel direction to the substrate are obtained in the rectangular parallelepiped.
It is desirable that the thickness of the insulative thin layers and the semiconductor or metal layers interposed between two insulative thin layers is equal to or smaller than 20 nm. Particularly, it is desirable that the insulative layers are thin. The thickness thereof is equal to or smaller than 10 nm, at the best 3 to 2 nm, for SiO
2
or SiN. It is not necessary to thin the semiconductor or metal layers so much and the thickness thereof is satisfactory if it is about 20 nm. Further, oxidization is made until the oxidization speed is equal to or smaller than one fourth, preferably one fifth, of a value in bulk of the semiconductor or metal to thereby obtain the super-fine structure stably. The side of the laminated layers may be etched instead of the oxidization, so that the above various structures may be formed.
The above another object is achieved by oxidizing the laminated layer pattern including semiconductor or metal thin layers and insulative thin layers
Chaudhuri Olik
Hitachi , Ltd.
Mattingly Stanger & Malur, P.C.
Wille Douglas A.
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