Method of making an article comprising an oxide layer on a...

Details Method of making an article comprising an oxide layer on a... Method of making an article comprising an oxide layer on a...

1998-07-24

2001-08-07

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S142000, C438S197000, C438S236000, C438S767000, C438S779000, C257S410000, C257S411000

Reexamination Certificate

active

06271069

ABSTRACT:

TECHNICAL FIELD
This invention pertains to methods of making articles that comprise an oxide layer on a GaAs-based semiconductor body, typically GaAs-based field effect transistors (FETs).
BACKGROUND OF THE INVENTION
GaAs-based transistors and circuits are used in, for instance, wireless communication apparatus, due inter alia to the relatively high electron mobility in GaAs, the availability of semi-insulating GaAs substrates, and the relative simplicity of the manufacturing processes.
Si-based metal oxide semiconductor (MOS) field effect transistors (FETs) are known, and are widely used. Among the advantages of Si-based MOS-FETs are simplicity, low power and low cost. The most common Si-based MOS-FET is the enhancement-type MOS-FET, which is “normally off” with zero gate voltage.
As is well known, an important factor in Si MOS-FET technology is the ease with which a high quality stable and controllable silicon oxide layer can be formed on the conventional (100) surface of a Si wafer. This includes a very low (e.g., 10
10
cm
−2
eV
−1
or less) surface state density at the Si/silicon oxide interface.
Much effort has been directed towards GaAs-based MOS-FETs. See, for instance, T. Mimura et al.,
IEEE Transactions on Electron Devices
, Vol. ED-27(6), p. 1147 (June 1980) for a review of early work. The authors of that paper concluded (p. 1154) that, although the main features of the results achieved so far are promising, “. . . some technological problems remain, including anomalous behavior of the dc and low-frequency operation of the devices. Undoubtedly, these problems are associated with the high density of surface states involved in the GaAs MOS system.” See also A. Colquhoun et al.,
IEEE Transactions on Electron Devices
, Vol. ED 25(3), p. 375 (March 1978), and H. Takagi et al.,
IEEE Transactions on Electron Devices
, Vol. ED 25 (5), p. 551 (May 1978). The former discloses a device that comprises an etched notch that defines the channel thickness. Such a non-planar structure would be relatively difficult to make repeatably, and thus is less desirable than a planar MOS-FET would be.
As pointed out by Mimura et al., the early devices suffered from poor gate oxide/GaAs interface quality, including a high density of interface states. In recent years, substantial effort has been directed at this problem.
For instance, U.S. Pat. No. 5,451,548 discloses formation of a Ga
2
O
3
film on GaAs by e-beam evaporation from a high purity single crystal of Gd
3
Ga
5
O
12
. See also U.S. Pat. No. 5,550,089, and U.S. patent application Ser. Nos. 08/408,678 and 08/741,010, which disclose GaAs/Ga
2
O
3
structures with low midgap interface state density. See also M. Passlack et al.,
Applied Physics Letters
, Vol. 69(3), p. 302 (July 1996) which reports on the thermodynamic and photochemical stability of low interface state density GaAs/Ga
2
O
3
/SiO
2
structures that were fabricated using in situ molecular beam epitaxy. Other pertinent publications are M. Passlack et al.,
Applied Physics Letters
, Vol. 68(8), p. 1099 (Febuarary 1996); and M. Hong et al.,
J. of Vacuum Science and Technology B
, Vol. 14(3), p. 2297, (May/June 1996).
However, despite the extensive effort by many researchers over many years, and the resulting large number of publications, to date it has not been possible, to the best of our knowledge, to fabricate GaAs-based MOS-FETs that can meet commercial requirements.
In the absence of a commercially viable GaAs-based MOS-FET technology, GaAs-based integrated circuits for instance require double supply voltages and have relatively high power consumption, resulting in turn in relatively short battery lifetime and requiring relatively complex circuitry in, for instance, battery-powered personal communication devices. Such ICs are of limited usefulness.
In view of the significant advantages that would attend availability of commercially acceptable GaAs-based MOS-FETs, it would be highly desirable to have available such devices, especially enhancement mode (normally “off”) MOS-FETs. This application discloses an exemplary process of making such devices that provides low gate oxide/semiconductor interface state density, and can preserve this low state density throughout the subsequent processing steps.
SUMMARY OF THE INVENTION
A currently preferred exemplary embodiment of the invention is a method of making an article that comprises a GaAs-based (e.g., GaAs or a ternary or quaternary III-V alloy that comprises Ga and As) semiconductor body having a major surface, and that further comprises a layer of oxide dielectric material disposed on the major surface.
The method comprises providing the semiconductor body, and forming the layer of oxide dielectric material on the major surface, said forming comprising completion (at a time t
m
) of a first monolayer of the oxide dielectric material on the major surface. The major surface is prepared (e.g., by MBE growth of a semiconductor layer on a substrate body, and/or by appropriate cleaning or cleaving in UHV) such that, at a given point (t
c
) in time the major surface is substantially atomically clean and substantially atomically ordered. A (100)-oriented surface is considered to be “substantially atomically clean” if surface coverage by impurity atoms is less than (typically substantially less than) 1% of a monolayer, preferably less than 0.1% of a monolayer. The degree of coverage by impurity atoms can be measured by a known technique (XPS). See, for instance, P. Pianetta et al.,
Phys. Rev. Letters
, Vol. 35 (20), p. 1356 (1975).
Furthermore, at least during the period from t
c
to t
m
, the semiconductor body is maintained in a reduced pressure atmosphere (typically UHV), the conditions (time, pressure, temperature, etc.) selected such that, at time t=t
m
, the coverage of the surface with impurity atoms is less than 1% of a monolayer. Exemplarily, this condition is typically met if the pressure p(t) is selected such that
∫
t
c
t
m
⁢
p
⁡
(
t
)
⁢
 
⁢
ⅆ
t
is at most 100 Langmuir. A “Langmuir” is a conventional measure of surface exposure, namely 1×10
−6
Torr seconds. In preferred embodiments the value of the integral is less than 50, even less than 10 Langmuir. It will be appreciated that p(t) is the pressure due to impurity species such as O
2
, CO, H
2
O, and does not include the pressure due to growth species or surface stabilizers such as As.
At time t=t
c
the surface is not only substantially atomically clean but also substantially atomically ordered. By a “substantially atomically ordered” (100) GaAs surface we mean herein a (100) GaAs surface exhibiting a 2×4 (or possibly 4×6 or other) RHEED (reflection high energy electron diffraction) pattern. Methods that can be used to produce a substantially atomically ordered (100) GaAs surface are known.
GaAs-based semiconductor/oxide interfaces formed according to our technique not only can have very low density of interface states (exemplarily <10
11
/cm
2
·eV) and low surface recombination velocity (exemplarily <10
4
cm/s), with inversion observed in both n-type and p-type material, but also have high thermochemical and photochemical stability. These values pertain to room temperature (20° C.). All of these advantageous properties are observed on (100)-oriented interfaces, and thus are directly applicable to electronic devices such as MOS-FETs.
The instant invention exemplarily is embodied in a method of making an article (e.g., an IC, or a personal communication device that comprises the IC) that comprises a GaAs-based MOS-FET having improved characteristics, including a low gate oxide/semiconductor midgap interface state density.
More specifically, the invention is embodied in a method of making an article that comprises a GaAs-based MOS-FET comprising a GaAs-based substrate having a major surface, two spaced apart regions of a first conductivity type extending from the major surface into the substrate (designated “source” and “drain”, respectively), a metal contact disposed on each of s

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