Method of making a transistor having a deposited dual-layer spac

Details Method of making a transistor having a deposited dual-layer spac Method of making a transistor having a deposited dual-layer spac

1995-12-11

1998-02-03

Bowers, Jr., Charles L.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438303, 438305, H01L 21336

Patent

active

057144133

ABSTRACT:
A transistor comprising a deposited dual-layer spacer structure and method of fabrication. A polysilicon layer is deposited over a gate dielectric, and is subsequently etched to form the polysilicon gate electrode of the transistor. Next, oxide is deposited over the surface of the gate electrode, followed by deposition of a second dielectric layer. Spacers are then formed adjacent to the gate electrode by etching back the second dielectric layer using a substantially anisotropic etch which etches the second dielectric layer faster than it etches the oxide.

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