Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-07-14
2002-03-19
Pham, Long (Department: 2123)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S149000, C438S151000, C438S152000, C438S162000, C438S163000, C438S164000, C438S289000, C438S291000
Reexamination Certificate
active
06358805
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and fabrication method, and more specifically, to a semiconductor device and fabrication method by which adjacent elements are insulated from one another by a buried insulating layer.
2. Description of Related Art
With advancements in large-scale integration of semiconductor devices, the distance between adjacent elements has become shorter. However, reducing the distance between adjacent elements can result in unwanted electrical junctions between the elements. For example, a latch-up may result from the formation of a parasitic bipolar junction transistor between NMOS and PMOS elements in a CMOS (Complementary Metal Oxide Semiconductor) device.
To overcome this problem, semiconductor devices have been designed with a SOI (Silicon On Insulator) structure. In a SOI structure, an insulating layer is formed on a semiconductor substrate, and a thin single crystal silicon layer is formed on the insulating layer. The thin single crystal silicon layer is used as a depletion region.
A semiconductor device having an SOI structure can be made by using an SIMOX (Separation by Implanted Oxygen) or BESOI (Bonded and Etchback SOI) substrate. To form the SIMOX substrate, impurities such as oxygen (O
2
) or nitrogen (N
2
) are ion-implemented into a semiconductor substrate to form a buried insulating layer. The BESOI substrate is produced by melting two semiconductor substrates having an insulating layer consisting of Si
3
O
2
, Si
3
N
4
or the like, and etching the combined substrate to a desired thickness.
As described above, the semiconductor device having an SOI structure can avoid unwanted electrical junctions between elements, such as the formation of a parasitic bipolar transistor, by isolating the semiconductor substrate from the single crystal silicon layer with an insulating layer to obtain pn-junction protection.
FIG. 1
is a cross section of a semiconductor device in accordance with the prior art.
Referring to
FIG. 1
, a buried insulating layer
13
is formed on a semiconductor substrate
11
, and depletion regions
15
(300 to 1500 Å thick) doped with p-type impurities are formed on the buried insulating layer
13
. The buried insulating layer
13
and the depletion regions
15
form an SOI structure. Layer
13
and region
15
are prepared by either an SIMOX (Silicon On Insulator) or a BE (Bonded and Etchback) method. If they are made by the SIMOX method, the semiconductor substrate
11
is p-type which is the same conductivity type as the depletion regions
15
. When produced using a BE method, the semiconductor substrate
11
may be p-type or n-type, irrespective of the conductivity type of depletion regions
15
.
A field oxide layer
17
defines the active region of elements and is formed in the depletion regions
15
. Field oxide layer
17
contacts the buried insulating layer
13
, rendering field oxide layer
17
electrically isolated from active regions adjacent to the active region of the element comprising the depletion regions
15
. A gate oxide layer
19
is formed on the depletion regions
15
. Gate
21
is formed on the gate oxide layer
19
. Both sides of the gate
21
, which is formed in the depletion regions
15
, are heavily doped with n-type impurities, such as arsenic (As), antimony (Sb) or phosphorus (P), to form an impurity region
23
that will function as source and drain regions. The depletion regions
15
between the impurity regions
23
will become a channel.
Because the above-described semiconductor device has depletion regions
15
on the buried insulating layer
13
that are between 300 to 1500 Å thick, applying OV to the gate
21
will determine the threshold voltage by depicting the channel comprising the depletion regions
15
under the gate
21
.
FIGS. 2A-2C
are flow diagrams illustrating a process for fabricating semiconductor devices according to prior art.
Referring to
FIG. 2A
, p-type depletion regions
15
are formed on the buried insulating layer
13
of a semiconductor substrate
11
having thickness of between 300 and 1500 Å. A field oxide layer
17
, defining the active regions of elements, is formed in predetermined portions on the depletion regions
15
by LOCOS (Local Oxidation of Silicon). The field oxide layer
17
is in contact with the buried insulating layer
13
. The buried insulating layer
13
and the depletion regions
15
are formed on the semiconductor substrate
11
using either SIMOX or BE methods. When the buried insulating layer
13
and the depletion regions
15
are made using the SIMOX method, the semiconductor substrate
11
is p-type, which is the same conductivity type as depletion regions
15
. If made using the BE method, the semiconductor substrate
11
can be either p-type or n-type, irrespective of the depletion regions
15
.
Referring to
FIG. 2B
, a gate oxide layer
19
is formed on the surface of the depletion regions
15
by heat oxidation. In addition, doped amorphous silicon or polysilicon is deposited on the field oxide layer
17
and the gate oxide layer
19
by chemical vapor deposition (hereinafter, referred to as “CVD”). Following the CVD, the amorphous silicon or polysilicon layer is patterned using a photolithographic process to leave only a predetermined portion on the depletion regions
15
, thereby producing gate
21
.
Referring to
FIG. 2C
, the depletion regions
15
are heavily doped with n-type impurities, such as arsenic (As), phosphorus (P) or the like. During their formation, gate
21
is used as a mask to create an impurity region
23
that will function as source and drain regions. The depletion regions
15
between the impurity regions
23
will become a channel.
In a conventional semiconductor device as described above, the buried insulating layer and the depletion regions are formed on the semiconductor substrate using the BE method. Thus, the depletion regions may not be uniform in thickness after an etchback process. Variations in the thickness of the depletion regions cause the capacitance of the depletion regions to be varied. Consequently, the threshold voltage of the channel is not constant. As the depletion regions become thinner, variations in the thickness of the depletion regions increase the variations in the threshold voltage of the channel to a greater degree.
SUMMARY OF THE INVENTION
An object of the present invention is to solve the problem described above and to create a semiconductor device and its fabrication method. This object is accomplished by making the threshold voltage of the channel constant, irrespective of the thickness of the depletion regions, thereby preventing the deterioration of element characteristics.
Another object of the present invention is to provide a semiconductor device having a constant channel threshold voltage, and its fabrication method.
To achieve these and other objects and advantages, and in accordance with the present invention, a semiconductor device includes a semiconductor substrate, a depletion region positioned above the semiconductor substrate, a buried insulating layer positioned between the semiconductor substrate and the depletion region, a field oxide layer positioned above the buried insulating layer and adjacent to the depletion region, a gate positioned above the first depletion region, a gate oxide layer positioned between the depletion region and the gate, impurity regions positioned on both sides of the gate, and a counter doping layer positioned under the channel of the depletion region.
In addition, the present invention includes a method of manufacturing a semiconductor device, including the steps of forming a buried insulating layer on a semiconductor substrate, forming a depletion region above the semiconductor substrate and above the buried insulating layer, forming a field oxide layer in a predetermined portion of the depletion region, forming a gate oxide layer on a surface of the depletion region, forming a gate on the field oxide layer and above the depletion region, formi
Son Jeong-Hwan
Yang Hyeong-Mo
Brairton Scott
LG Semicon Co. Ltd.
Pham Long
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