Method of making a smaller geometry high capacity stacked DRAM d

Details Method of making a smaller geometry high capacity stacked DRAM d Method of making a smaller geometry high capacity stacked DRAM d

1996-03-01

1999-08-31

Niebling, John F.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438253, 438381, 438396, 438738, H01L 218242

Patent

active

059465662

ABSTRACT:
A DRAM having a theoretical cell layout efficiency of 100% and a density of up to four gigabits DRAM is obtained without sacrificing the storage capacitor values. This accomplishment is achieved by introducing landing pads in layout and obtaining narrow widths down to 1000 .ANG. and small spaces down to 700 .ANG.. The DRAM has active isolations, word lines, cup-shaped vertical capacitor walls, and bit lines. The process for forming small dimensions having this narrow width, narrow wall and the small space in ranges down 800 .ANG. comprises depositing a form material on the surface of a product material. A portion of the form material is removed by RIE etching by using the lithography technique. A layer of masking material is deposited over the form material and product material, the layer of masking material having a thickness correlating to said desired width of product material. Masking material is removed by vertical RIE until the form material is exposed, leaving a predetermined width of masking material. Portions of the product material which are not protected by the masking material are removed to leave a desired width of product material corresponding to the width of the masking material. The corresponding process can be used to form spacings of corresponding dimensions.

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