Method of making a semiconductor package including stacked...

Details Method of making a semiconductor package including stacked... Method of making a semiconductor package including stacked...

2002-08-20

2003-11-18

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Chip mounted on chip

C257S686000, C257S777000, C257S782000, C257S783000, C438S109000, C438S118000

Reexamination Certificate

active

06650019

ABSTRACT:

BACKGROUND
1. Technical Field
This invention pertains to semiconductor packaging in general, and in particular, to a method and apparatus for malting semiconductor packages with stacked dies.
2. Related Art
The increasing demand for electronic devices that are smaller, lighter, and yet more functional has resulted in a concomitant demand for semiconductor packages that have smaller outlines and mounting footprints, yet which are capable of increased component packaging densities.
One approach to satisfying this demand has been the development of techniques for stacking the semiconductor dies, or “chips,” contained in the package on top of one another. Examples of die-stacking techniques may be found, for example, in U.S. Pat. No. 5,323,060 to R. Fogel, et al.; U.S. Pat. No. 5,815,372 to W. N. Gallas; Re. No. 36,613 to M. B. Ball; U.S. Pat. No. 5,721,452 to R. Fogel, et al.; and, Japanese Patent Disclosures 62-126661, 4-56262, 63-128736, and 10-256470.
FIGS. 1 and 2
are respectively a top plan and a cross-sectional side elevation view of a semiconductor package
10
incorporating a pair of stacked dies
14
and
16
in accordance with the respective methods and apparatus of the prior art. The package
10
illustrated is a ball grid array (“BGA”) type of package, so-called because of the balls of solder
19
formed on the bottom surfaces of the substrate
12
, which function as input/output terminals of the package. The package
10
includes a conventional interconnective substrate
12
and a first semiconductor die
14
mounted on a top surface of the substrate. A second die
16
has been “stacked,” i.e., mounted, on top of the first die
14
. The dies
14
and
16
typically include a plurality of input/output wire bonding pads
34
located at the peripheral edges of their respective top, or “active,” surfaces.
The substrate
12
may comprise a flexible resin tape, a rigid fiber-glass/copper sheet laminate, a co-fired ceramic coupon, or a metal lead frame, all of known types in the industry, depending on the particular type of semiconductor package
10
at hand. The connective substrate
12
illustrated in the BGA package
10
shown in
FIGS. 1 and 2
comprises a layer
20
(see
FIG. 2
) of an insulative material, e.g., a polyimide resin film, laminated between conductive layers
22
,
24
of a metal, e.g., copper or aluminum, that comprise the respective top and bottom surfaces of the substrate.
The conductive layers
22
,
24
are typically patterned, e.g., by photolithography and etching techniques, to define wire bonding pads
26
and circuit traces
27
in the top layer
22
, and solder ball mounting lands
28
in the bottom layer
24
. The terminal pads
26
and traces
27
are typically connected to the solder ball lands
28
through the thickness of the insulative layer
20
by “vias”
30
, i.e., plated-through holes in the layers. Either or both of the conductive layers
22
,
24
may be coated over with an insulative “solder mask” (not illustrated) that has openings in it through which the respective wire bonding pads
26
and/or solder ball lands
28
are exposed, and which serve to prevent bridging between the pads and/or lands by accidental solder splashes.
In an alternative embodiment, the substrate
12
may comprise a metal lead frame (not illustrated) having a die-mounting paddle centrally supported within a matrix of radially extending leads. In this embodiment, the dies
14
and
16
wire bond to inner ends of the leads of the lead frame, rather to bonding pads located on the substrate, and the formed leads serve as the input/output terminals of the package
10
.
In the embodiment illustrated, the first die
14
is conventionally mounted to the top surface of the substrate
12
with, e.g., a layer of an adhesive or an adhesive film
13
, and then electrically connected to the substrate by a plurality of fine, conductive wires
38
, typically gold or aluminum, that connect the pads
34
on the die to the pads
26
on the substrate.
The second die
16
is mounted on the top surface of the first die
14
with an adhesive layer
15
comprising a second layer of an adhesive or a double-backed adhesive film that has a lateral perimeter
17
(shown by the dotted outline in
FIG. 1
) positioned entirely within the central area of the top surface of the first die and completely inside of the peripheral wire bonding pads
34
thereon. That is, the adhesive layer
15
does not contact or cover either the wire bonding pads
34
or the conductive wires
38
bonded thereto. The adhesive layer
15
positions the second die
16
sufficiently far above the first die
14
to prevent the former die from contacting the conductive wires
38
bonded to the latter die and shorting them out, and thus defines a peripheral space
19
(
FIG. 2
) between the two dies that extends around the entire perimeter
17
of the spacer. The second die
16
is then wire bonded to the substrate
12
in the same fashion as the first die
14
. One or more additional dies (not illustrated) can then be stacked in tandem on top of the second die
16
using the same technique.
After the dies
14
and
16
are wire bonded to the substrate
12
, the dies, substrate, and conductive wires
38
are “overmolded” with a dense, monolithic body, or “mold cap”
60
(shown by dotted outline in
FIG. 2
, omitted for clarity in FIG.
1
), of plastic, typically a filled epoxy resin, that encapsulates the packaged parts and protects them from environmental elements, particularly moisture.
In a stacked-die package
10
of the type illustrated in
FIGS. 1 and 2
, the dies
14
and
16
are wire bonded sequentially, typically with automated wire bonding equipment employing well-known thermal-compression or ultrasonic wire bonding techniques. As shown in
FIG. 2
, during the wire bonding process, the head
62
of a wire bonding apparatus applies a downward pressure on a conductive wire
38
held in contact with a wire bonding pad
34
on the die to effect a weld or bond of the wire to the pad.
Since the wire bonding pads
34
are located in the peripheral area of the respective top surfaces of the two dies, this entails the application, in the direction of the arrow shown in
FIG. 2
, of a relatively large, localized force to that area of the die. This does not present a problem with the bottom die
14
, as it is supported from below by the substrate
12
and the adhesive layer
13
. However, in the case of the second, top die
16
, its peripheral portion is cantilevered out over the peripheral portion of the bottom die
14
by the adhesive layer
15
, and is therefore unsupported from below. As a consequence, the top die
16
can crack or fracture during the wire bonding procedure, as illustrated in
FIG. 2
, which results in the entire assembly being scrapped.
Another problem that can result with the prior art die stacking techniques also relates to the peripheral space created between the opposing surfaces of the first and second dies
14
and
16
by the adhesive layer
15
and the plastic molding material used to form the body
60
that encapsulates the dies. In particular, the encapsulant material penetrates into the peripheral space during the molding process and forms a “wedge” between the two dies. If the encapsulant material has a different thermal coefficient of expansion than that of the adhesive spacer
15
, it is possible for this wedge to expand within the peripheral space
19
with large changes in temperature of the package
10
, and thereby fracture one or both of the dies
14
and
16
, again resulting in a defective package that must be scrapped.
BRIEF SUMMARY
This invention provides a simple, inexpensive method for making a semiconductor package with stacked dies that eliminates fracturing of the dies during the wire bonding process or as a result of incompatible thermal expansions. The method permits the use of ultra-thin dies having the same size, and does not require the use of support pillars.
In one embodiment, the method includes the provision of a substrate, which may be either a conventional

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