Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-05-19
1999-11-09
Chaudhuri, Olik
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438264, H01L 218247
Patent
active
059813423
ABSTRACT:
A semiconductor component, in particular an EEPROM, and a production method therefor, avoid an avalanche breakdown from a buried channel to a substrate through the use of a special lateral dopant profile in the buried channel, in which a peripheral zone of the buried channel has a higher effective doping than a region located below a tunnel window. The lateral dopant profile is produced through the use of a compensation implantation with dopant atoms of the conduction type opposite that of the buried channel.
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Adan, A.O. et al., A scaled .6/spl mu/m high speed PLD technology using single-poly EEPROM's, Custom Integrated Circuits Conference, Proceeding of the IEEE, pp. 55-58, 1995.
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Kakoschke Ronald
Sedlak Holger
Chaudhuri Olik
Greenberg Laurence A.
Lerner Herbert L.
Mae Daniel
Siemens Aktiengesellschaft
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