Method of making a non-volatile semiconductor memory device

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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Details

C257S315000, C257S316000, C257S317000

Reexamination Certificate

active

06977202

ABSTRACT:
Disclosed is a fabrication method for a non-volatile semiconductor memory device that comprises a pattern forming step in which by using a first mask layer and a second mask layer formed in a common lithography step as masks, a pattern is formed from a second layer, a third layer, a fourth layer, a sixth layer and a protection layer in a laminated substrate having, in a memory cell area, a sequential lamination of a first layer for forming a first insulating layer, the second layer for forming a floating gate, the third layer for forming an intergate insulating layer, the fourth layer for forming a control gate and a first mask layer, and having, in a logic area, a sequential lamination of a fifth layer for forming a second insulating layer, the sixth layer for forming a logic gate, the protection layer for protecting the sixth layer at the time of forming the control gate and a second mask layer. The fabrication method can fabricate a non-volatile semiconductor memory device by forming layers in a self-aligned manner with respect to a gate electrode while minimizing an alignment error and a chip size.

REFERENCES:
patent: 6368907 (2002-04-01), Doi et al.
patent: 6617632 (2003-09-01), Taniguchi et al.
patent: 7-193198 (1995-07-01), None

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