Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2006-04-19
2008-10-28
Le, Thao X. (Department: 2892)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
Reexamination Certificate
active
07442591
ABSTRACT:
A semiconductor device has two types of multi-gate transistors, N channel and P channel, in which each type has a bottom gate and a top gate. The bottom gate and the top gate of the N channel transistors are chosen to be of a metal or metals that are for optimizing the performance of the N channel transistors. Similarly, the bottom gate and the top gate of the P channel transistors are chosen to be of a metal or metals that are for optimizing the performance of the P channel transistors.
REFERENCES:
patent: 5273921 (1993-12-01), Neudeck et al.
patent: 6828181 (2004-12-01), Chen et al.
patent: 2005/0282318 (2005-12-01), Dao
Vinet et al; “Bonded Planar Double-Metal-Gate NMOS Transistors Down to 10 nm”; IEEE Electron Device Letters, vol. 26, No. 5, May 2005.
Balconi-Lamica Michael
Clingan, Jr. James L.
Freescale Semiconductor Inc.
Le Thao X.
Trice Kimberly
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