Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1996-05-13
1997-06-24
Niebling, John
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
257358, 257360, 438454, H01L 21265
Patent
active
056416970
ABSTRACT:
A p-type high concentration doped region is formed in a p-type semiconductor substrate between a n-type doped region as part of an input protection circuit and another n-type doped region as part of internal circuitry. A plate is divided into two over the high concentration doped region. The high concentration doped region suppresses generation of a parasitic MOS transistor with the plate for a gate, one of the n-type doped regions for a source, and the other for a drain.
REFERENCES:
patent: 4602267 (1986-07-01), Shirato
patent: 4692781 (1987-09-01), Rountree et al.
patent: 4893157 (1990-01-01), Miyazawa et al.
patent: 4937639 (1990-06-01), Yao et al.
patent: 5027252 (1991-06-01), Yamamura
patent: 5158899 (1992-10-01), Yamagata
patent: 5183773 (1993-02-01), Miyata
patent: 5406105 (1995-04-01), Lee
patent: 5436484 (1995-07-01), Iwai et al.
patent: 5446303 (1995-08-01), Quill et al.
patent: 5449939 (1995-09-01), Horiguchi et al.
patent: 5449940 (1995-09-01), Hirata
patent: 5514612 (1996-05-01), Rao et al.
Niebling John
Nippon Steel Semiconductor Corporation
Pham Long
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