Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-06-04
1999-09-28
Dutton, Brian
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438156, 438270, H01L 2100, H01L 2184, H01L 21336
Patent
active
059602775
ABSTRACT:
A merged power device structure, of the emitter-switching type, in which the emitter of the bipolar power transistor has a minimum-width pattern which is aligned to the trenches of a trench control transistor. Thus the current density of the bipolar is maximized, since the emitter edge length per unit area is increased. The parasitic base resistance of the bipolar can also be reduced.
REFERENCES:
patent: 4487639 (1984-12-01), Lam et al.
patent: 4868626 (1989-09-01), Nakazato et al.
patent: 4881119 (1989-11-01), Paxman et al.
patent: 4893160 (1990-01-01), Blanchard
patent: 4935799 (1990-06-01), Mori et al.
patent: 5118635 (1992-06-01), Frisina
patent: 5247200 (1993-09-01), Momose et al.
patent: 5304821 (1994-04-01), Hagino
patent: 5380670 (1995-01-01), Hagino
patent: 5410170 (1995-04-01), Bulucea et al.
patent: 5424231 (1995-06-01), Yang
patent: 5471075 (1995-11-01), Shekar et al.
Blanchard, "A Power Transistor With an Integrated Thermal Feedback Mechanism," Massachusetts Institute of Technology (1970). No Month.
Tukune, et al., "Spontaneous Polysilicon and Epitaxial Silicon Deposition," J. Electrochem. Soc., vol. 142, No. 5 (1995). No Month.
Dutton Brian
Galanthay Theodore E.
Jorgenson Lisa K.
STMicroelectronics Inc.
Szuwalski Andre M.
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