Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-06-17
2001-05-22
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S785000
Reexamination Certificate
active
06235572
ABSTRACT:
TITLE OF THE INVENTION
A semiconductor device, a method of manufacturing the semiconductor device, and an apparatus for manufacturing the semiconductor device.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a manufacturing technique thereof, and particularly to a technique advantageously applicable to a semiconductor device having a DRAM (Dynamic Random Access Memory).
Memory cells of a DRAM are arranged on cross points between a plurality of word lines and a plurality of bit lines which are arranged in a matrix layout on a main surface of a semiconductor substrate, and each memory cell contains a memory cell selection MISFET (Metal Insulator Semiconductor Field Effect Transistor) and an information storage capacitor connected in series with the MISFET. The memory cell selection MISFET is formed in an active region surrounded by an element isolation region and mainly consists of a gate oxide film, a gate electrode formed to be a part of a word line, and a pair of semiconductor regions forming a source and a drain. A bit line is provided above the memory cell selection MISFETs and is electrically connected with one of the source and drain common to two memory cell selection MISFETs. The information storage capacitor is provided also above the memory cell selection MISFETs and is electrically connected to the other one of the source and drain.
Japanese Patent Application Laid Open No. 7-7084 discloses a DRAM having a capacitor over bitline structure in which an information storage capacitor is provided above a bit line. In the DRAM described in this reference, the information storage capacitor consists of a lower electrode (storage electrode) processed of a cylindrical shape, a capacity insulating film and an upper electrode (plate electrode). By processing the lower electrode into a cylindrical shape, the surface area of the lower electrode is increased, and the reduction of storage charge amount (Cs) of the information storage capacitor is compensated for scale down of the memory cell. A multi layered insulating film comprising a silicon oxide film and a silicon nitride film are used as a capacity insulating film.
However, the surface area of the lower electrode is reduced as integration and scale down of a DRAM progress. It is consequently difficult to ensure a sufficient storage charge amount with a capacity insulating film made of a multi layered film comprising a silicon oxide film and a silicon nitride film. Meanwhile, if the film thickness of the capacity insulating film is reduced for maintaining a sufficient storage charge amount, a leakage current will be increased between upper and lower electrodes with the result that the refresh characteristic will be deteriorated or the reliability of DRAM. Hence, there has occurred a demand for a method of maintaining a necessary storage charge amount with a film thickness sufficient for reducing a leakage current, and various methods have been proposed.
In one of those methods, a high-dielectric material or a ferroelectric material is used for a capacity insulating film, and the effective film thickness of the capacity insulating film is reduced where the effective film thickness is calculated as an equivalent silicon oxide film, thus obtaining a sufficient capacity value. A typical insulating film thereof is a tantalum oxide film. The technique of using a tantalum oxide film is described in, for example, “Extended Abstracts of the 1993 International Conference on Solid State Device and Materials, Makuhari, pp853 to 855, and pp862 to 864, or “Extended Abstracts (The 43rd Spring Meeting, 1996); The Japan Society of Applied Physics and Related Societies”, page 728.
SUMMARY OF THE INVENTION
It is difficult to deposit a tantalum oxide film at a high temperature since an tantalum oxide film is generally formed by a CVD method using an organic tantalum gas. Therefore, the tantalum oxide film as deposited is in an amorphous state and must be subjected to a thermal treatment to crystallize the film, in order to obtain a capacity insulating film with a high dielectric constant. Meanwhile, there is a method of improving the quality of a tantalum oxide film by a thermal treatment or plasma treatment in an oxidation atmosphere at about 400° C., in order to avoid a heat treatment at a high temperature.
Of the tantalum oxide films described above, the tantalum oxide film improved by a heat treatment or plasma treatment has a lower dielectric constant than a crystallized tantalum oxide film and is therefore disadvantageous for high integration of a DRAM. The film quality of a tantalum oxide film not crystallized may be deteriorated or the reliability of the DRAM may be reduced by a heat treatment (for example, at 400 to 600° C.) or the like for proceeding conductance between a wire after forming an information storage capacitor and a contact portion of a wire or substrate thereunder. Meanwhile, a crystallized tantalum oxide film has been subjected to a sufficiently high temperature during a heat treatment for the crystallization (for example, at 750° C.) and is therefore less deteriorated by a heat treatment to be performed later. In addition, a crystallized tantalum oxide film has a dielectric constant, which is twice higher than that of an amorphous material, and is therefore advantageous for high integration of a DRAM. Thus, a tantalum oxide film used for a capacity insulating film is desirable to crystallize in view of reliability of thermal treatment or of applying for high integration.
However, a crystallized tantalum oxide film is a thin poly-crystal film, and the film includes a grain boundary. The grain boundary may form a path for a leakage current between upper and lower electrodes formed with a tantalum oxide film inserted therebetween. In particular, it has been found from studies and discussions by the present inventors that the leakage current tends to increase if a polycrystalline silicon film having a surface including granular silicon (Hemispherical Silicon Grain) is used for the lower electrode. To realize high integration and a DRAM with high reliability, the following technique is required which is capable of reducing the leakage current in a lower electrode structure as described above.
In addition, if a crystallized tantalum oxide film is used, the film thickness of a capacity insulating film can be increased within the allowance of design standpoint by using the high dielectric constant thereof. Increase of the film thickness is a countermeasure for reducing the leakage current. However, if the film thickness of the tantalum oxide film is increased, the stress of the crystallized tantalum oxide film is increased thereby causing a leakage current at the boundary of crystal.
Further, it has also been found through studies and discussions by the present inventors et al. that increase of the film thickness causes deterioration of the surface morphology of the crystallized tantalum oxide film. The deterioration of the surface morphology means an occurrence of a portion where the distance between the upper and lower electrodes is short in fine scale, and the possibility of leakage or insulation break-down increases at this portion. In particular, such a portion where the distance between electrodes is short also becomes a boundary of crystal with a high possibility. It is considered that this portion causes further increase of a leakage current.
Meanwhile, a silicon oxide film is normally used as a gate insulating film in a MISFET. However, the film thickness of the gate insulating film needs to be reduced in accordance with scale down of the MISFET. As long as the silicon oxide film used as the gate insulating film, a tunneling current flows between the substrate and the gate electrode so that the MISFET does not operate properly if the film thickness is reduced to about several nm.
An object of the present invention is to provide a capacity insulating film which has heat resistance, causes a less leakage current, and achieves a high withstand voltage.
Another object of the present i
Iijima Shinpei
Kunitomo Masato
Antonelli Terry Stout & Kraus LLP
Chaudhari Chandra
Hitachi , Ltd.
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