Method of making a low power SRAM

Details Method of making a low power SRAM Method of making a low power SRAM

1997-11-21

1999-12-28

Monin, Jr., Donald L.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438213, 438231, H01L 2170

Patent

active

060080809

ABSTRACT:
An SRAM is formed having the six transistor cell. The pull down transistors are formed so that no arsenic is implanted into the drains of the pull down transistors so that the drains of the pull down transistors are doped only by phosphorus implantation. The sources of the pull down transistors are doped with an LDD configuration of phosphorus ions and then a further implantation of arsenic ions is performed. This can conveniently be accomplished by providing an opening in the mask used to implant impurities into the source/drain regions of the ESD protection circuit.

REFERENCES:
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patent: 5547888 (1996-08-01), Yamazaki
patent: 5625217 (1997-04-01), Chau et al.
patent: 5710449 (1998-01-01), Lien et al.
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patent: 5780912 (1998-07-01), Burr et al.
patent: 5789787 (1998-08-01), Gardner
patent: 5804477 (1998-09-01), Lien et al.
Sasaki et al., A 9-ns 1-Mbit Cmos SRAM, IEEE Journal of Solid State Circuits vol. 24, No. 5, pp. 1219-1225, Oct. 1989.

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