Method of making a floating gate memory cell

Details Method of making a floating gate memory cell Method of making a floating gate memory cell

2000-05-15

2001-05-15

Dang, Trung (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S257000

Reexamination Certificate

active

06232185

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to fabrication technologies of a semiconductor device and, in particular, to a method of fabricating a split gate non-volatile floating gate memory cell.
2. Description of the Prior Art
Recently, high-density flash memories have been receiving much attention for application to the silicon files used in still cameras and hand-held, portable mass-storage computing devices. One of the most important factors is the size of the memory cells. Shrinkage of cell size and a reduction in fabrication steps reduce the cost of these memories, and at the same time, increase the functionality of the memories.
Conventional fabrication processes require sufficiently spaced electrical contacts to the source and drain regions from the gate of the transistor to ensure that the source, drain and gate remain electrically isolated when manufacturing tolerances are taken into account. The spacing is a function of the alignment and critical dimensions such that under worst case manufacturing tolerances, the contacts do not touch the polysilicon gate.
One such conventional method of establishing self-aligned contacts involved oxidizing the polycrystalline silicon gate at a high temperature to provide insulation between the contacts and the gate. However, the temperatures associated with forming oxidation barriers cause diffusion of the dopants in the source and drain regions.
This diffusion changes the dimensions of the source and drain regions and thus prevents this approach from being used when integrated circuits are fabricated using one micron and sub-micron fine line geometries. In addition, high temperature oxidation according to prior art self-aligning contact schemes causes oxide to grow along the outer edge of the interface between the gate and the gate oxide, effectively increasing the thickness of the gate oxide in that area. Consequently, the threshold voltage of the transistor will be higher along the edge of the gate than along its center. Thus, the current drive of the transistor will be significantly reduced.
A split gate non-volatile floating gate memory cell fabricated according to a conventional method, using a LOCOS process, is shown in FIG.
1
. As shown in
FIG. 1
, floating gates
61
have a top surface formed of a cap layer
62
which is comprised of a silicon dioxide film. The cap layers
62
are used as etching barriers. Side-wall spacers
63
composed of silicon dioxide are formed on the side walls of the gates
61
. Active region
64
is formed in the semiconductor between thick field oxide regions
65
created for purposes of isolating. An inter-poly dielectric layer
66
a
composed of silicon dioxide is formed on the gates
61
for the purpose of isolating.
The conventional method comprises the steps of forming the field oxide
65
on the semiconductor substrate
67
. Then a gate oxide layer
68
and a polysilicon layer
61
are respectively formed on the field oxide
65
and semiconductor substrate
67
. A silicon dioxide layer
62
is formed on the polysilicon layer
61
. Then, a photoresist
69
is patterned on the polysilicon layer
61
and silicon dioxide layer
62
using an etching process to etch the polysilicon layer
61
and the silicon dioxide layer
62
. After the etching process, the cap layers
62
and gate electrodes
61
are formed, as shown in
FIG. 2
a.
Referring now to
FIG. 2
b
, a silicon dioxide layer
63
a
is deposited by using an atmosphere pressure chemical vapor deposition (APCVD) on the gates
61
and cap layers
62
over the semiconductor substrates
67
. An isotropic etching is used to form sidewall spacers
63
of the gates
61
, as shown in
FIG. 2
c
. Next, an inter-poly dielectric layer
66
a
is formed by using low pressure chemical vapor deposition (LPCVD). Another layer
50
of polysilicon is deposited on the dielectric layer
66
a
. Finally, a photoresist
69
is patterned, as shown in
FIG. 2
d
, and a dry etching is performed to form the contact window after which the photoresist
69
is removed, as shown in
FIG. 2
e.
Yet another conventional method of fabricating a self-aligned cell is disclosed in U.S. Pat. No. 5,668,757, which is herein incorporated by reference. In that reference, a self-aligned memory cell is fabricated by forming an isolated active device region on a semiconductor substrate of a first conduction type. Then, a first insulation film is formed on the active device region of the semiconductor substrate. A select gate is formed through the first insulation film on the active device region of the substrate which defines the first channel region. Then, a third insulation film is formed on the active device region which is not covered by the select gate, and a second insulation film is formed on the select gate. A floating gate is then formed through the third insulation film on the semiconductor substrate which defines the second channel region, and through the second insulation film on the select gate. A fourth insulation film is then formed on the select gate and the floating gate. A control gate is formed through the fourth insulation film on the select gate and the floating gate. Source and drain regions are formed by doping the source and drain regions, respectively, by ion implantation of a second conductor type. Finally, the source region is additionally formed which is overlapped by a portion of the floating gate, by lateral diffusion of the ion implantation in the source region through thermal diffusion.
SUMMARY OF THE INVENTION
Three methods for forming three types of non-volatile memory cells are disclosed. The three types are completely self-aligned, partially self-aligned, and non-self aligned. All three cells, however, comprise a select gate, a floating gate, and a control gate. The completely self-aligned method comprises the steps of forming an active region, between two isolation regions in a semiconductor substrate of a first conductivity type. A first insulating film is formed on the substrate. A first polysilicon layer is formed on the first insulating film. A second insulating film is formed on the first polysilicon layer. The second insulating film and the first polysilicon layer are etched at one end to form an etched first polysilicon layer, wherein the etched first polysilicon layer has a portion overlying a first channel region of the active region. A second polysilicon layer is formed over the first insulating film and the second insulating film. A plurality of sacrificial masking film strips are formed on the second polysilicon layer with each strip being over an active region and between a pair of isolation regions. The second polysilicon layer is etched using the sacrificial masking film strips. A third insulating film is formed on the second polysilicon layer. A third polysilicon layer is formed over the third insulating film. A masking layer is applied to the third polysilicon layer. The masking layer and the third polysilicon layer are etched to form the control gate. The control gate is used to etch the first and second polysilicon layers, to form the select gate and the floating gate.
In the partially self-aligned method, the third polysilicon layer and the second polysilicon layer are self-aligned etched. Thereafter, however, the second insulating layer over the first polysilicon layer is used as an etch stop in the etching of the second polysilicon layer. Thus the second polysilicon layer is not self-aligned with the first polysilicon layer.
In the non-self-aligned method, the second insulating layer over the first polysilicon layer is used as an etch stop in the etching of the second polysilicon layer. Thus the second polysilicon layer is not self- aligned with the first polysilicon layer. Further, the third insulating layer over the second polysilicon layer is used as an etch stop in the etching of the third polysilicon layer. Thus the third polysilicon layer is not self- aligned with the second polysilicon layer.
Finally, additional methods are disclosed for the formation of the foregoing type

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