Method of making a flash memory cell

Details Method of making a flash memory cell Method of making a flash memory cell

1996-05-28

1997-04-15

Niebling, John

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438594, H01L 21265, H01L 2170, H01L 2700

Patent

active

056209134

ABSTRACT:
A flash memory EEPROM transistor is formed on a surface of a semiconductor substrate. In portions of the substrate, at the surface thereof, a doped source region and a doped drain region are formed with a channel region therebetween. A tunnel silicon oxide dielectric layer is formed over the semiconductor substrate aside from the source region. Above the source region is formed a gate oxide layer which is thicker than the tunnel oxide layer. Above a portion of the tunnel oxide dielectric layer, over the channel region and above a portion of the gate oxide layer is formed a stacked-gate structure for the transistor comprising a floating gate layer, an interelectrode dielectric layer, and a control gate layer. The source region is located on one side of the stacked gate structure with one edge of the source region overlapping the gate structure. The drain region which is located on the other side of the stacked gate structure with one edge thereof overlapping the gate structure.

REFERENCES:
patent: 4295265 (1981-10-01), Horiuchi et al.
patent: 4611308 (1986-09-01), Lonky
patent: 5444279 (1995-08-01), Lee
patent: 5482879 (1996-01-01), Hong

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