Method of making a dynamic random access memory device...

Details Method of making a dynamic random access memory device... Method of making a dynamic random access memory device...

1999-09-13

2001-08-07

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S626000, C438S692000, C438S253000, C438S254000, C438S396000, C438S397000

Reexamination Certificate

active

06271124

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and a method for fabricating the same, and more particularly, to a dynamic random access memory (DRAM) device with a capacitor-over-bitline structure which can improve a global unevenness on a wafer by a chemical-mechanical polishing process and a method for fabricating the same.
2. Description of the Related Art
With the high integration of a DRAM device, a reduction of a cell in size is inevitable. As the area of the cell is reduced, it is important to ensure the capacitance of a capacitor. Various approaches have been tried to ensure the capacitance of the capacitor for reducing the thickness of a dielectric film using a material having a high dielectric constant as the dielectric film, or increasing the area of a storage node. As another means of increasing the capacitance of the capacitor, an initial plane cell capacitor structure can be changed to a stacked or trench capacitor structure. In the stacked capacitor structure, the effective area of the storage node, can be increased by utilization of a cylindrical capacitor or a fin type capacitor.
A capacitor-under-bitline (CUB) structure is one in which the capacitor is formed before the bitline is formed. This structure can be changed to a capacitor-over-bitline (COB) structure in which the capacitor is formed after the bitline is formed. The COB structure has the superior advantage of increasing the capacitance of the capacitor within a limited area because it is possible to form the capacitor irrespective of a margin of a bitline process. Since the COB structure has the capacitor formed over the bitline, the size of the storage node can be maximized, and is limited only by the lithography process, and thus the large capacitance of the capacitor can be ensured.
Referring to
FIG. 1
, there is shown a DRAM device with a conventional COB structure before the capacitor is formed. A gate electrode
16
of a transistor is formed together with a gate insulating layer
14
over a semiconductor substrate
10
in which an active region and an isolation region are distinguished by a field oxide layer
12
. Source and drain regions
18
of the transistor are formed on substrate
10
on both sides of the gate electrode
16
. An insulating layer
20
with a self-aligned contact exposing the source and drain regions
18
is formed over substrate
10
, and transistor. A pad conductive layer
22
of an impurity-doped polysilicon layer is formed on the self-aligned contact. Generally, since the COB structure has the transistor, the bitline and an interlayer insulating layer formed under the storage node, an aspect ratio of a buried contact for electrically connecting the storage node to the source region of the transistor is increased. Therefore, the contact may be not opened. In order to easily form the buried contact and a bitline contact for electrically connecting the drain region of the transistor with the bitline, the conductive layer
22
serving as a landing pad is formed on the active region, that is, the source and drain regions of the transistor. Thus, the aspect ratios of the contacts are reduced.
A first interlayer insulating layer
24
consisting of an insulating material such as an oxide layer is then formed over the substrate
10
including the pad conductive layer
22
. The first interlayer insulating layer
24
insulates the transistor from the bitline and has the bitline contact (not shown) exposing the drain region of the transistor. A bitline
26
connected with the drain region of the transistor through the bitline contact is formed on the first interlayer insulating layer
24
. A second interlayer insulating layer
28
of the insulating material such as a BPSG (borophosphosilicate glass) is formed on the bitline
26
. The second interlayer insulating layer
28
insulates the bitline from the storage node of the capacitor. The second interlayer insulating layer
28
is planarized by an etch-back process. Although not shown in the drawing, the storage node of the capacitor is formed on the second interlayer insulating layer
28
. In this case, since the storage node is formed only on a memory cell region, the height of the boundary between the memory cell region and a peripheral region is high. That is, since the storage node is not formed on the peripheral region for driving the cell and a core region for connecting blocks of the cell with each other, the memory cell region, the core region and the peripheral region greatly differ in their absolute height. When the height of the storage node becomes higher in order to increase the capacitance, it is difficult to adjust a focus of any one of the memory cell region, the core region and the peripheral region in a subsequent exposing process for forming a contact and a metal wire because the respective focuses of those regions differ from each other.
Before the storage node of the capacitor is formed, there is a difference “a” in the height between the memory cell region, the core region and the peripheral region due to the transistor and the bitline
26
, as indicated in FIG.
1
. If the capacitor is formed over the substrate, the difference in height between the memory cell region, the core region and the peripheral region will be larger. Therefore, it is very difficult to ensure the margin of depth of the focus in a subsequent exposing process.
To solve such a focus problem, the region having the lowest height should be raised. As one example, there is a method for depositing an oxide-series layer to a considerably thick thickness and etching the layer to fill a portion having the difference in height. Although this method has the effect of reducing the difference in height between adjacent regions (hereinafter, this difference is referred to as the local unevenness), it has little effect on the reduction of the difference in height between regions having a width equal to twice or more wider than the thickness of the deposited oxide-series layer (hereinafter, this difference is referred to as the global unevenness).
As another method, a flowable film such as a spin-on glass (SOG) is used. However, there can be quality problems in the film, a problem related to a subsequent processes, etc. A method for covering a region having low height with a photoresist and etching a higher region may be also used. However, this method has a disadvantage in that it includes a number of additional process steps, and thus it is difficult to apply that method to mass production.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a semiconductor memory device with a COB structure, which can improve a global unevenness on a wafer by using a chemical-mechanical polishing process.
It is another object of the present invention to provide a method for fabricating the above-described semiconductor memory device.
In one aspect of the present invention, there is provided a semiconductor memory device with a capacitor-over-bitline structure including: a transistor having a gate electrode formed on a gate insulating layer on a semiconductor substrate and having source and drain regions formed on the surface of the substrate and separated from each other by the gate electrode; a first interlayer insulating layer formed over the substrate and transistor; a bitline formed over the first interlayer insulating layer; and a second interlayer insulating layer formed over the substrate and the bitline for insulating the bitline from a storage node of a capacitor; whereby a surface of the second interlayer insulating layer is planarized by a chemical-mechanical polishing (CMP) process so as to be substantially parallel to a surface of the substrate including the bitline. Preferably, the semiconductor memory device further includes an insulating layer formed on the second interlayer insulating layer. Preferably, the first interlayer insulating layer has a contact for connecting the drain region of the transistor with the bitline.
In another aspect of the

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