Method of making a DRAM cell with stacked trench capacitor

Details Method of making a DRAM cell with stacked trench capacitor Method of making a DRAM cell with stacked trench capacitor

1990-03-16

1991-11-19

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 38, 437 47, 437 60, 437203, 437233, 437235, 437919, H01L 2170

Patent

active

050666088

ABSTRACT:
A semiconductor device and a manufacturing method therefor are disclosed, the semiconductor device including a field oxide layer selectively formed on a semiconductor substrate for defining an active region; an electrically insulated gate electrode; a source and a drain region; a trench formed in the semiconductor substrate; an impurity-doped region formed at the surface of the trench; a first insulating layer; a second conductive layer; a dielectric film; a third conductive layer; a fourth conductive layer; an etch blocking layer; a fifth conductive layer. The manufacturing method comprises a plurality of processes for forming the above mentioned parts by applying various processes. According to the present invention, as both the impurity-doped polycrystalline silicon layer of the upper portion of the transistor and the inside of the trench including the impurity-doped region are simultaneously used as the first electrode of the capacitor, the surface area of the capacitor electrode can be made larger.

REFERENCES:
patent: 4794563 (1988-12-01), Maeda
patent: 4910566 (1990-03-01), Ema
patent: 4951175 (1990-08-01), Kurosawa et al.
Watanabe, "Stacked Capacitor Cells for High Density Dynamic RAMS", IEDM Digest, 1988, pp. 600-603.

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