Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1996-12-12
1998-10-20
Trinh, Michael
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438229, H01L 218238
Patent
active
058245782
ABSTRACT:
A method of making a complementary metal oxide semiconductor field effect transistor (CMOSFET) using liquid phase deposition. At first, a P-type silicon substrate is prepared, on which are formed a field oxide layer, a P-well, an N-well and a gate oxide layer. Next, a first polysilicon layer is formed. After doping the first polysilicon, a tungsten silicide layer is formed on the first polysilicon layer. Then, the first polysilicon layer and the tungsten silicide layer are patterned to form the polycide gate electrodes. With a mask shielding the area designated to be the N-channel FET, a P.sup.- type ion implant is performed. Then, a first silicon dioxide layer is formed by liquid phase deposition, followed by an anisotropic etching to form the first sidewall spacers. Then, a P.sup.+ type ion implant is performed. A second silicon dioxide layer is again formed by liquid phase deposition. Now, after removing the mask, an N.sup.- type ion implant is performed using the second silicon dioxide layer as a mask. Next, the second sidewall spacers are formed by depositing and etching back a layer of tetraethoxysilanes dielectric layer. Then, an N.sup.+ type ion implant is performed to form the N.sup.+ doped areas. After a boronphosphosilicate glass layer is deposited on the field oxide layer, the second silicon dioxide layer and the device area, the CMOSFET is completed.
REFERENCES:
patent: 5270233 (1993-12-01), Hamatake
patent: 5521106 (1996-05-01), Okabe
Mosel Vitelic Inc.
Trinh Michael
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