Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1998-02-24
2001-01-09
De Cady, Albert (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
06173426
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method of locating faults occurring in an LSI (Large Scale Integrated Circuit) and, more particularly, to a method of narrowing down multiple faults occurring in a CMOS (Complementary Metal Oxide Semiconductor) circuit.
Conventional methods available for narrowing down the location of a fault in an LSI by CAD (Computer Aided Design) simulation estimate the location on the basis of information indicative of an error occurring at an output terminal. One of the conventional methods is a fault simulation method using a fault dictionary. The fault simulation method compares, while defining a fault in each block of an inside circuit, an output terminal, an output value and a test pattern number at which a fault is detected with data derived from actual failed samples, thereby estimating a fault. Another conventional method, generally referred to as a back tracing method, traces a logic from an output terminal toward an input terminal in the reverse direction on the basis of an output terminal, an output value and a test pattern number at which an error has been detected. Specifically, the back tracing method inputs a preselected signal to the input terminal of an LSI. When the resulting signal appearing on the output terminal of the LSI differs from an expected value, the method picks up, among signals spreading from the output terminal toward the input terminal, a signal carrying a fault and thereby estimates the location of a fault. After defining a fault at the estimated location, the method again executes logic simulation in order to verify coincidence between the estimated fault and the actual fault. It is a common practice with the back tracing method to examine a plurality of output error locations and narrow down a fault while limiting a false fault signal on the basis of a combination of the above locations.
However, the problems with the conventional methods are that analysis is not practicable with an LSI having multiple faults therein, and that the amount of simulation data is too huge to render the methods practical. The analysis of an LSI with multiple faults is not practicable unless the number of multiple faults is known. Specifically, because error data on the output terminal alone cannot show how many faults exist, the analyst must estimate the number of faults by referencing the error data on the output terminal. Therefore, if the estimated number of errors is wrong, the analyst executes simulation with the wrong number of errors, resulting in an incorrect result of detection.
More specifically, the fault simulation method using a fault dictionary can deal only with a stuck-at fault (stuck-at-0 or stuck-at-1) model, i.e., it cannot simulate open faults. This kind of method therefore lacks in general-purpose applicability as to the location of a fault mode. This is because faults to be dealt with by fault simulation are modeled logical faults, but open errors are not definite in logic. Moreover, the number of faults to be defined must be sequentially defined for all signal lines constituting a circuit, resulting in an impractical amount of data. It is generally understood that the number of faults (V0) to be defined is proportional to the third to fourth power of the number (L) of circuit devices constituting an LSI, i.e., ln(VO)∝(3~4)·In(L).
The back tracing method cannot determine the number of faults occuring in a circuit because it relies only on information relating to an output terminal error. Further, while this kind of method can narrow down the location of an error only if a plurality of output error terminals exist, it assumes only a single fault. In addition, because signals spread from the output terminal toward the input terminal, a prohibitive number of false faults are detected and prevent the actual fault from being located. Therefore, it is difficult to narrow down a fault with the back tracing method alone. A current trend is toward a method linked with an EBT (Electron Beam Tester) or similar physical analysis implement and excluding false fault locations from candidates by obtaining a non-contact potential contrast image or a logical operation waveform, as reported at, e.g., the LSI Testing Symposium.
Technologies relating to the present invention are disclosed in, e.g., Masaru Sanada (inventor of the present invention) “EVALUATION AND DETECTION OF CMOS-LSI WITH ABNORMAL IDDQ”, Microelectronics and Reliability, Vol. 35, No. 3, pp. 619-629, 1995, and Japanese Patent Laid-Open Publication Nos. 6-313791 and 7-146341.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide an LSI fault locating method capable of narrowing down multiple faults of an LSI easily and rapidly with a minimum amount of data and without regard to output terminal errors, and thereby determining the number of faults and the locations where they occurred.
A method of detecting a fault occurring in an LSI of the present invention includes the step of detecting, among blocks which are basic logic circuit units constituting the LSI, a fault block by executing a logical operation with each of the blocks by using block-by-block logical operation information and test vector numbers causing an Iddq value, which is a leak current at a quiescent state of the logical operation of the LSI, to exceed a preselected value. The locations of multiple faults are narrowed down by using logic information particular to the fault block and corresponding to the test vector numbers causing an Iddq error to occur.
REFERENCES:
patent: 5550841 (1996-08-01), O'Brien
patent: 5790565 (1998-08-01), Sakaguchi
patent: 5850404 (1998-12-01), Sanada
patent: 5864566 (1999-01-01), Sanada
patent: 5889789 (1999-03-01), Sanada
patent: 6-313791 (1994-11-01), None
patent: 7-146341 (1995-06-01), None
Masaru Sanada, “Evaluation and Detection of CMOS-LSI with Abnormal IDDQ”,Microelectronics and Reliability, vol. 35, No. 3, 1995, pp. 619-629.
Abraham Esaw
Cady Albert De
NEC Corporation
Sughrue Mion Zinn Macpeak & Seas, PLLC
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