Method of isolation by active transistors with grounded gates

Details Method of isolation by active transistors with grounded gates Method of isolation by active transistors with grounded gates

1996-05-23

1998-12-15

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438430, 438655, H01L 21763

Patent

active

058496149

ABSTRACT:
An isolation gate structure is formed between active areas on a P-type semiconductor substrate. The isolation structure includes a thick gate oxide layer over which is formed a P-doped polycrystalline silicon layer. The polycrystalline silicon layer is electrically connected to the substrate, by buried contact if desired, and can further be electrically connected to a source region formed within the active area. The polycrystalline silicon layer and substrate are connected to ground potential, thus preventing current flow between active areas.

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