Computer-aided design and analysis of circuits and semiconductor – Design of semiconductor mask or reticle
Reexamination Certificate
2011-01-04
2011-01-04
Lin, Sun J (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Design of semiconductor mask or reticle
C716S051000, C716S053000, C716S054000, C716S055000
Reexamination Certificate
active
07865866
ABSTRACT:
A method of precisely inspecting the entire surface of a mask at a high speed in consideration of optical effects of the mask. The method includes designing a target mask layout for a pattern to be formed on a wafer, and extracting an effective mask layout using an inspection image measured from the target mask layout using an aerial image inspection apparatus as a mask inspection apparatus. The effective mask layout is input to a wafer simulation tool for calculating a wafer image to be formed on the wafer. Optical effects of the mask are detected by comparing the target mask layout with the effective mask layout.
REFERENCES:
patent: 7512927 (2009-03-01), Gallatin et al.
patent: 7703069 (2010-04-01), Liu et al.
patent: 2005-026360 (2005-01-01), None
patent: 2002-0079975 (2002-10-01), None
patent: 2006-0099708 (2006-09-01), None
patent: 2006-0131860 (2006-12-01), None
English language abstract of Japanese Publication No. 2005-026360.
English language abstract of Korean Publication No. 2006-0099708.
English language abstract of Korean Publication No. 2006-0131860.
Baik Hyun-Joo
Choi Sun-Young
Ji Min-Kyu
Kim Hee-Bom
Lin Sun J
Muir Patent Consulting, PLLC
Samsung Electronics Co,. Ltd.
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