Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-11-04
2001-06-26
Trinh, Michael (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S305000, C438S585000, C438S592000
Reexamination Certificate
active
06251737
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing a metal-oxide-semiconductor (MOS) transistor.
2. Description of the Related Art
In the manufacturing of deep submicron devices, the level of integration is increased. Hence, line width, contact area and junction depth of all devices are reduced. To improve the quality of devices and to lower transmission delay due to an increase in electrical resistance and capacitor (RC-delay), silicide layers are usually formed over the MOS transistors. The silicide layers are formed over the polysilicon gate and the source/drain terminals so that contact resistance at these junctions is lowered. Since there is no need to perform photolithographic operation, the step of forming silicide layers over the terminals of MOS transistors is often referred to as a self-aligned silicide (Salicide) process. Materials for forming a self-aligned silicide layer include titanium silicide (TiSi
x
) and cobalt silicide (CoSi
x
). Because titanium silicide has the advantage of easy control during fabrication, it is one of the most frequently employed silicide materials.
Titanium silicide layer can be further classified structurally as being in a C
49
high-resistance metastable phase (C
49
-TiSi
2
) or in a C
54
low-resistance thermodynamically stable phase (C
54
-TiSi
2
). To form a titanium silicide layer, a first stage rapid thermal heating process is carried out so that titanium in a titanium layer reacts with silicon in a silicon layer. After the first stage thermal process, C
49
phase titanium silicide and a small amount of C
54
phase titanium silicide are formed. The unreacted titanium layer is removed, and then a second stage rapid thermal heating operation is carried out at an elevated temperature. In the second stage thermal operation, the high-resistance C
49
phase titanium silicide within the titanium silicide layer is gradually transformed into a low-resistance C
54
phase titanium silicide.
C
49
phase titanium silicide has a low formation temperature but its electrical resistance is high. In contrast, C
54
phase titanium silicide has a low electrical resistance but its formation temperature is high. In general, a rapid thermal process for transforming the high-resistance C
49
phase titanium silicide in a titanium silicide layer into low-resistance C
54
phase titanium silicide must be employed. Furthermore, in order to form a thick and uniform silicide layer, processing temperature must be raised or the period of heating must be extended.
As dimensions of the polysilicon gate are gradually reduced due to miniaturization, the formation temperature of the C
54
phase titanium silicide is increased because of the narrow line effect. The narrow line effect refers to the increase in phase transformation temperature resulting from a decrease in line width.
In other words, as line width becomes smaller, temperature required to transform high-resistance C
49
phase titanium silicide into low-resistance C
54
phase titanium silicide is increased. However, raising the rapid thermal processing temperature to obtain C
54
phase titanium silicide may result in some instability in the resulting silicide layer. Hence, too high a processing temperature is unsuitable for forming small dimensional devices. Moreover, reaction temperature is difficult to control and may result in lateral growth of the silicide layer. In addition, as the level of integration continues to increase and separation between neighboring devices continues to decrease, lateral growth can easily lead to bridging between a gate terminal and a source/drain terminal. To prevent such bridging, an upper limit to the temperature for forming a metal silicide layer must be set. However, this will result in an intensification of the narrow line effect. Hence, a higher resistance will be formed at the polysilicon gates.
SUMMARY OF THE INVENTION
The invention provides a method for increasing gate surface area for depositing silicide material. A silicon substrate having device isolation structures therein is provided. A stack of sacrificial layers comprising a first sacrificial layer at the bottom, a second sacrificial layer in the middle and a third sacrificial layer at the top is formed over the silicon substrate. A gate opening is formed in the stack of sacrificial layers to expose a portion of the substrate. A portion of the second sacrificial layer exposed by the gate opening is next removed to form a horizontal side opening on each side of the gate opening. The gate opening together with the horizontal side opening form cross-shaped hollow space. A gate oxide layer is formed at the bottom of the gate opening. Polysilicon material is deposited to fill the gate opening and the side openings, thereby forming a cross-shaped gate polysilicon layer. The third, the second and the first sacrificial layers are removed. A metal silicide layer is formed over the gate polysilicon layer.
This invention also provides a method of manufacturing a semiconductor device on a silicon substrate having device isolation structures therein. The method includes forming a stack of sacrificial layers over the silicon substrate. The stack comprises of a first sacrificial layer at the bottom, a second sacrificial layer in the middle and a third sacrificial layer on top. A gate opening is formed in the stack of sacrificial layer to expose a portion of the substrate. A portion of the second sacrificial layer exposed by the gate opening is removed, thereby forming a horizontal side opening on each side of the gate opening. These horizontal side openings together with the gate opening form a cross-shaped hollow space. A gate oxide layer is next formed at the bottom of the gate opening. Polysilicon material is deposited to fill the cross-shaped hollow space, thereby forming a gate polysilicon layer having a cross-shaped profile. The gate polysilicon layer includes a vertical main body together with a pair of horizontal arms, one on each side of the main body. The third sacrificial layer, the second sacrificial layer and a portion of the first sacrificial layer are removed so that a portion of the first sacrificial layer remains under the arms of the gate polysilicon layer. A heavy implantation is carried out to form a heavily doped source/drain region in the silicon substrate on each side of the gate polysilicon layer. The residual first sacrificial layer under the arms is removed. A light implantation is next carried out to form a lightly doped source/drain region in the silicon substrate under each arm. A silicide process is conducted to form a silicide layer over the gate polysilicon layer and the heavily doped source/drain regions. Insulating material is deposited over the silicon substrate to form an insulation layer so that spacers filled with air are also formed under the arms. The air spacers serve to reduce parasitic capacitance between the gate terminal and neighboring source/drain regions.
Aside from increasing the area coverage of silicide layer over the gate terminal, the formation of an air spacer underneath each arm is capable of lowering the dielectric constant. Hence, parasitic capacitance between the gate terminal and the source/drain region is reduced and operating speed of the device is increased. Furthermore, by forming the heavily doped source/drain regions before forming the lightly doped source/drain regions, a lower annealing temperature can be used. Consequently, shallow junctions are formed in the lightly doped source/drain regions and the short-channel effect is minimized.
In the invention, the gate structure with a cross-shaped sectional profile is formed, thereby increasing effective surface area for depositing silicide. With more silicide material on the gate, narrow line effect is prevented and contact resistance at the gate terminal is reduced. Furthermore, the air space under each arm of the cross forms a spacer that can reduce
Charles C.H. Wu & Associates
Trinh Michael
United Microelectronics Corp.
Wu Charles C.H.
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