Method of improving vertical BJT gain

Details Method of improving vertical BJT gain Method of improving vertical BJT gain

1999-05-19

2001-01-16

Nguyen, Tuan H. (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S234000

Reexamination Certificate

active

06174760

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a complementary metal-oxide semiconductor CMOS, and more particularly, to a bipolar junction transistor BJT for compatible high gain gated lateral BJT and more quality device.
2. Description of the Prior Art
Recently, demand for semiconductor devices has rapidly increased owing to widespread use of integrated electronic circuit. In particularly, static random access memory (SRAM) has become a basic and elementary component used in integrated circuits (ICs), such as semiconductor memory devices. More particularly, as more than hundreds or thousands of electrical components are integrated into the ICs, a means for scaling down the dimension of the SRAM and reducing fabrication cost has become imperative.
The conventional CMOS SRAM cell essentially consists of a pair of cross-coupled inverters as the storage flip-flop or latch, and a pair of passes transistors as the access devices for data transfer into and out of the cell. Thus, a total of six Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) or four MOSFETs plus two very high resistance load devices are required for implementing a conventional CMOS SRAM cell. However, to achieve high packing density, it is the usual practice to reduce the number of the devices needed for realizing a CMOS SRAM cell or the number of the devices for performing the Write/Read operation. Especially for the case of very high resistance load devices, increased process complexity, extra masks, and high fabrication cost are required for forming the undoped polysilicon layers or the Thin Film Transistor (TFT) on the oxide and thus saving the chip area; however, the corresponding product yield is not high. Therefore, more efforts are needed to further reduce the areas occupied by the chip while improving the production yield.
In the realm of microwave transistors, both bipolar and field effect transistors, higher frequency performance has required narrower and narrower line width. Bipolar IC technology has traditionally been the choice technology for high-speed application. This is partly due to the face that in this technology transit time is determined by the base width of the bipolar device. And the base width not being determined by lithography as is the case with the channel length of MOS devices, but rather by the difference between the impurity diffusion profiles of the emitter and base. In the BJT device structure, a reduction in line width corresponding reduction in the overall bases area. With the overall objective of reduction of capacitance between the junctions, in particular the emitter base junction, the result is shorter emitter base charging times, as well as a reduced transit time across the base. Time translates into an increase in overall device switching speeds and frequency characteristics.
The single material BJT, traditionally silicon, has been the choice technology for high-speed application. This is due in part to the fact that this technology enables transit times that are determined by the base width of the bipolar device.
Designer needs to use BJT in Bandgap Reference and Voltage Regulator circuits. It is more important to make BJT fabrication on CMOS chip. Vertical PNP (P
+
/N-well/P-sub) is used as a BJT compatible with current CMOS technology. Due to higher well concentration is need when shrinking device gate length, vertical BJT gain (p) is getting smaller. Table 1 (Appendix) shows BJT current gain in three different generation technologies.
For the foregoing reasons, there is a need for a method forming higher BJT gain in deep sub-quarter micro CMOS technology. Appendix:
TABLE 1
Vertical PNP &bgr; gain in different technology
N well X
j
P
+
X
j
Rs-N well
Vertical
Technology
(&mgr;m)
(&mgr;m)
(&OHgr;/square)
PNP &bgr; gain
0.45
2.7
0.25
724
5
0.35
2.9
0.18
700
3.5
0.25
1.8
0.18
400
2.1
SUMMARY OF THE INVENTION
In accordance with the present invention, a vertical Bipolar Junction Transistor BJT method is provided for higher BJT gain and more quality device.
Another purpose of the present invention is to have P-type specie, which is only implanted in BJT region. Using different implanted dosage and energy to form a higher BJT gain. For example, P-type ions of the first conductive type is implanted into the emitter of BJT inside the semiconductor substrate, wherein concentration of the implanted P-type ions is about 1E
13
/cm
3
to 5E
15
/cm
3
and energy of the implanted P-type ions is about 20K eV to 60K eV. And depth of the Ptype implant must be deeper than source/drain implant. Therefore, different implanted dosage and energy will result in different improvements. The method is efficient and compatible with CMOS technology.
In one embodiment, the present invention is provided for higher BJT gain and more quality device. Providing a semiconductor substrate incorporating a device, wherein the device is defined metal oxide semiconductor (MOS) region and bipolar junction transistor (BJT) region. Conductivity-type well region is formed on the semiconductor substrate, and then a gate oxide layer is formed on the conductivity-type well region of MOS region. Consequently, a polysilicon layer is deposited on the gate oxide layer of MOS region. Using photolithographic and etching process to define a gate structure, wherein the polysilicon layer is used as the gate of MOS region. Further implanting ions of a first conductive type into the semiconductor substrate of MOS region. A first dielectric layer is forming on sidewall of the gate, wherein the first dielectric layer is used as a spacer of MOS region. Sequentially, a first photoresist layer is formed over semiconductor substrate of BJT region to define an emitter of BJT. Then implanting second ions of the first conductive type into the semiconductor substrate of MOS region to form source/drain regions by using said spacer as a mask. Simultaneously implanting second ions of the first conductive type into the semiconductor substrate to form the emitter of BJT. Sequentially, a second photoresist layer is deposited over the device of the MOS region. Finally, implanting third ions of the first conductive type into the emitter of BJT inside the semiconductor substrate.


REFERENCES:
patent: 4120707 (1978-10-01), Beasom
patent: 5780329 (1998-07-01), Randazzo et al.
patent: 5866446 (1999-02-01), Inoh
patent: 6030864 (2000-02-01), Appel et al.
patent: 6071767 (2000-07-01), Monkowski et al.

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