Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1999-06-30
2002-08-13
Gulakowski, Randy (Department: 1746)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S701000, C438S717000, C438S719000, C438S724000, C438S723000, C438S725000, C438S736000, C438S737000, C438S738000, C438S740000, C438S978000
Reexamination Certificate
active
06432832
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to the fabrication of semiconductor integrated circuits (IC's). More particularly, the present invention relates to methods and apparatuses for etching through an IC's layer stack to produce substantially similar profile angles between narrow and wide etched features.
During the manufacture of a semiconductor-based product, for example, a flat panel display or an integrated circuit, multiple deposition and/or etching steps may be employed. By way of example, one method of etching is plasma etching. In plasma etching, a plasma is formed from the ionization and dissociation of process gases. The positively charged ions are accelerated towards the substrate where they, in combination with neutral species, drive the etching reactions. In this manner, etched features such as vias, contacts, or trenches may be formed in the layers of the substrate.
Recently, shallow trench isolation (STI) has grown in popularity as a preferred method for forming a trench that can, among other applications, electrically isolate individual transistors in an integrated circuit. Electrical isolation is needed to prevent current leakage between two adjacent devices (e.g., transistors). Broadly speaking, conventional methods of producing a shallow trench isolation feature include: forming a hard mask (e.g., nitride and pad oxide) over the targeted trench layer, patterning a soft mask (e.g., photoresist) over the hard mask, etching the hard mask through the soft mask to form a patterned hard mask, and thereafter etching the trench layer (e.g., silicon) to form the shallow trench isolation feature. Subsequently, the soft mask is removed in a separate process (i.e., ashed, wet etched, etc.) and the shallow trench isolation feature is back filled with a dielectric material.
FIGS. 1A-1C
are cross section views of the conventional process steps that are used to form shallow trench isolation features. Referring initially to
FIG. 1A
, there is shown a typical layer stack
10
that is part of a substrate or semiconductor wafer. (not drawn to scale for ease of illustration). A silicon layer
12
is located at the bottom of layer stack
10
. A pad oxide layer
14
is formed above silicon layer
12
and a nitride layer
16
is formed above pad oxide layer
14
. In most situations, the pad oxide layer is used as the interlayer that is disposed between the nitride layer and the silicon layer. Furthermore, in order to create a patterned hard mask with pad oxide layer
14
and nitride layer
16
, a photoresist layer
18
is deposited and patterned using a conventional photolithography step over nitride layer
16
. After patterning, soft mask openings
20
(narrow) and
22
(wide) are created in photoresist layer
18
to facilitate subsequent etching. The above-described layers and features, as well as the processes involved in their creation, are well known to those skilled in the art.
Following the formation of layer stack
10
, nitride layer
16
and pad oxide
14
are subsequently etched to create a hard mask, which includes a narrow hard mask opening
24
and a wide hard mask opening
26
, as seen in FIG.
11
B. The hard mask openings are used to pattern the trench during etching of the silicon layer. For the most part, etching stops after reaching silicon layer
12
, however, a small portion on the surface of silicon layer
12
is typically etched away during the etching of pad oxide layer
14
. Moreover, a gas chemistry that includes CF
4
is typically used to facilitate etching through the nitride and pad oxide layers. Typically, the CF
4
chemistry etches the side walls of narrow hard mask openings anisotropically (i.e., straight down). Correspondingly, the profile angle between the narrow hard mask opening and the wide hard mask opening tend to have limited angular variation. Moreover, photoresist layer
18
(e.g., soft mask) is partially eroded during the reaction (e.g., etching), as shown.
Furthermore, during etching, a passivating film
21
is typically built up along the side walls of the etched features. The passivating film is formed from the etch products of the etched layers (e.g., photoresist, nitride and pad oxide). Typically, when the etch products come off the surface being etched, they are re-energized in the plasma and as a result have a mean free path or trajectory wherein the etch products collide with surfaces inside the processing chamber. Because the carbon in the photoresist tends to contribute, or promote sticking of the chemical components, the etch products tend to stick to the first surface they come in contact with, where they form a deposit (e.g., passivating film).
Further still, because the line of sight of the etched products is greater on wide features than on narrow features more collisions typically will occur on the side walls of the wide features. By way of example,
FIG. 1B
shows a first line of sight
34
for the narrow feature and a second line of sight
36
for the wide feature. As shown, the line of sight of the narrow feature has a substantially smaller grouping of angles than the line of sight of the wide feature. Additionally, there is typically less etch byproducts per unit of vertical surface area in the narrow spaces relative to the wide spaces. As a result, passivating film
21
tends to be thicker on wide hard mask opening
26
than on narrow hard mask opening
24
.
Once a hard mask opening is created through nitride layer
16
and pad oxide layer
14
, silicon layer
12
is etched to form shallow trench isolation features, for example, a narrow feature
30
and a wide feature
32
, as shown in FIG.
1
C. Typically, a gas chemistry that includes Cl
2
and/or HBr is used to facilitate etching through the silicon layer.
Furthermore, during the silicon etch, narrow feature
30
forms a first profile angle
38
and wide feature
32
forms a second profile angle
40
. The profile angle is measured as the angle formed by the etch side wall with a plane parallel to the top surface of the silicon layer. As a general rule, first profile angle
38
is typically closer to 90 degrees than second profile angle
40
. While wishing not to be bound by theory, it is believed that the profile angles for the silicon trench are controlled to a significant degree by the deposition of etch products from the plasma. That is, the thicker the passivating film the more gradual the slope of the profile angle (i.e., less vertical). Therefore, because the wide features tend to have a thicker passivating film than the narrow features, the wide features will tend to have a less vertical slope than the narrow features. By way of example, the angular variation between the profile angles of the narrow and wide features may typically be between 8 and 12 degrees.
Moreover, it is contemplated that because the trenches are part of the active structure their relative profiles may have an influence on the behavior of the active structure. It is believed that, profile disparity between features may alter device performance, especially in logic type of devices. For example, it may alter the speed of electron flow, which will cause adverse timing issues. Additionally, it may effect subsequent processing steps such as CMP (e.g., due to leveling problems after back filling), which may contribute to problems in further steps.
Still further, in recent years, when designing features, the design criteria has been to design towards the narrow features and then apply that criteria to the wide features. However, to achieve greater circuit density, modern integrated circuits are scaled with increasingly narrower design rules. By way of example, it is not uncommon to employ design rules as small as 0.18 microns or even smaller in the fabrication of some high density integrated circuits. As the devices are packed closer together, it is important to minimize the angular difference between features as much as possible.
In a typical process flow, the substrate is taken out of the processing chamber after etching to remove the photoresist. Typically, th
Melaku Yosias
Miller Alan J.
Beyer Weaver & Thomas LLP
Gulakowski Randy
Lam Research Corporation
Smetana Jiri
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