Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-01-05
2001-08-14
Crane, Sara (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S412000
Reexamination Certificate
active
06274915
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to semiconductor devices and more particularly to semiconductor devices in which the gate electrodes are composed of polysilicon with dopant depletion.
BACKGROUND
The design principles and fabrication of conventional MOS transistors are well known. Typically, an MOS transistor includes a channel region in a semiconductor substrate between a doped source region and a doped drain region in the substrate. A conductive gate electrode overlies the channel region, physically separated from the substrate by a thin silicon oxide insulating layer, termed the gate oxide.
MOS transistor performance is characterized by a drive current, which is the current flowing between source and drain regions when the transistor is conducting, and by circuit delay. For desirable performance, the goal is to maximize the drive current and to minimize circuit propagation delay for a given geometry.
Polysilicon is frequently used as the material for forming the gate electrode for MOS transistor devices. Polysilicon adheres well to gate oxides and is able to withstand the environmental changes during processing steps subsequent to the gate electrode being formed. An impurity species, or dopant, is incorporated in the polysilicon to make the polysilicon conducting. The dopant species used in conventional transistor processing include phosphorous and arsenic, for creating n-type polysilicon, and boron or BF
2
, for creating p-type polysilicon. Conventionally, a high dopant concentration is used to reduce the degree of depletion in the polysilicon gate. The degree of depletion is the thickness of the region in the polysilicon gate adjacent the gate oxide layer, in which space charge develops when the transistor device is conducting. The conventional approach is to minimize the level of depletion, which may result in an improvement in drive current.
However, maximizing the dopant concentration to minimize the level of depletion can have additional effects. The higher the doping level, the more defects are created in the polysilicon. When boron is used as a dopant, higher concentrations of boron increase the likelihood of boron penetration, the tendency of boron to diffuse out of the polysilicon gate into the gate oxide layer, which undesirably can affect device reliability. Furthermore, minimizing the level of depletion does not necessarily improve propagation delay. Under certain conditions, as depletion levels are decreased, circuit delay can actually increase.
Thus, it would be desirable to provide a design for an MOS transistor that simultaneously increases drive current and device speed, and minimizes circuit delay. It would further be desirable to provide a method of manufacturing such a device.
SUMMARY
A design for an MOS transistor deliberately uses depletion in a polysilicon gate electrode to improve circuit performance. According to an embodiment of the present invention, appropriate levels of depletion in the gate electrode, larger than conventional levels, simultaneously provide desired drive current while minimizing circuit delay. According to another aspect, circuit performance is improved by adjusting doping levels in the channel region to maintain a threshold voltage at the same level as that which is achieved with minimum depletion in a polysilicon gate electrode.
The degree of depletion in the gate electrode is increased by adjusting the doping level of the polysilicon gate downward. Dopant concentrations of between 1×10
19
and 5×10
19
atoms/cm
3
are advantageously used. Alternatively, the degree of depletion in the gate electrode is increased by using amorphous silicon as the gate electrode material instead of polysilicon. In yet another alternative, the benefits of a higher degree of depletion in the gate electrode are achieved by increasing the thickness of a polysilicon gate electrode relative to the horizontal dimensions of the device. The ratio of the thickness of the polysilicon gate electrode to the channel length, which may be taken as a characteristic device feature size, ranges between 0.6 and 1.5.
According to another embodiment of the present invention, a method of AS fabricating an MOS device including a polysilicon gate electrode with increased depletion is provided. A self-aligned process is used in which the polysilicon gate, the source region, and the drain region, are simultaneously implanted to dopant concentrations of between 1×10
19
and 5×10
19
atoms/cm
3
. The light dopant concentration is beneficial in providing desirably shallow source and drain regions and in limiting boron penetration problems in the case of boron as a dopant.
REFERENCES:
patent: 3615934 (1971-10-01), Bower
patent: 3673471 (1972-06-01), Klein et al.
patent: 5674788 (1997-10-01), Wristers et al.
patent: 5757204 (1998-05-01), Nayak et al.
patent: 5783469 (1998-07-01), Gardner et al.
patent: 5789780 (1998-08-01), Fulford et al.
Bang David
Hao Ming-yin
Krishnan Srinath
Maszara Witold
Advanced Micro Devices , Inc.
Crane Sara
Saxon Roberta P.
Skjerven Morrill & MacPherson LLP
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