Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-04-22
2001-06-19
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
Reexamination Certificate
active
06248662
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the fabrication of integrated circuit, and more particularly, to a method of improving the gap filling characteristics of dielectric layer and forming void-free dielectric layer.
2. Description of the Prior Art
In the fabrication of integrated circuit, dielectric materials are employed in many applications such as covering semiconductor structures, forming passivation layer and forming isolation layer. In specially, when packing density of integrated circuit is increased and multi-layer structure is required, dielectric materials are employed to separate alternate layers and then some structures such as inter metal dielectric (IMD) and inter layer dielectrics (ILD) are formed.
In general, dielectric material is formed over a surface that some semiconductor structures are located in and on it. Obviously, not only these semiconductor structures are covered by dielectric layer but also these gaps that locate between portions of semiconductor structures are filled by dielectric layer. No matter how, the formation of dielectric layer is subject to arrival angle effect and shadowing effect. That is, the forming rate of dielectric is faster in the corner region of said semiconductor structures than other regions of said semiconductor structures. Thus, there are voids inside dielectric layer and the density of voids are direct proportion to aspect of said gaps.
FIG. 1A
to
FIG. 1C
illustrate the formation of voids. First, as shown in
FIG. 1A
, the top surface
11
of semiconductor substrate
10
is planarized and a plurality of semiconductor devices are formed in and on semiconductor substrate
10
. Then a plurality of semiconductor structures
12
are formed on top surface
11
and there are gaps
13
between portions of semiconductor structures
12
. Second, a first dielectric layer
14
is formed over the top surface
11
and then semiconductor structures
12
are covered by it. Obviously, as
FIG. 1B
shows, when the aspect of gap
13
is small then only overhangs
15
are formed in the corner parts of semiconductor structures
12
, but when the aspect of gap
13
is large then there is void
16
inside gap
13
. Third, second dielectric layer
17
is sequentially formed over first dielectric layer
14
, where possible material of second dielectric layer
17
comprises material of first dielectric layer
14
. Obviously, as shown in
FIG. 1C
, not only the top surface of second dielectric layer
17
is non-uniform where dips
18
are located above the gaps
13
but also there are voids
16
inside the second dielectric layer and the location of voids
16
correspond to the location of gap
13
.
According to the previous discussion, it is obvious that when aspect of gap
13
is large enough, there are voids
16
within the gap
13
or above the gap
13
and the quality of the integrated circuit is degraded by these voids
16
. Thus, it is desired to find a gap filling technique that will fill a gap without the presence of any void and then the formed integrated circuit is void-free.
SUMMARY OF THE INVENTION
Correspondingly, the primary object of the present invention is to propose a method for improving the gap filling characteristics of the dielectric layer to form a void-free dielectric layer.
A further object of the present invention is to propose a method that improves the gap filling and step coverage characteristics of the dielectric layer by implantation.
Moreover, a specific object is to propose a method which improves gap filling of the borophosph tetraethyl-orthosilica (BPTEOS) layer by application of SiOF and B
2
O
5
.
In order to accomplish these objects of the invention, a method for improving gap filling characteristics of dielectric layer by implantation is proposed. The provided method comprises the following steps:
First, semiconductor devices are formed in and on a semiconductor substrate wherein the top surface of said semiconductor substrate is planarized.
Second, semiconductor structures are formed overlying said top surface wherein gaps are located between portions of said semiconductor structures, then a first dielectric layer is formed to cover these semiconductor structures.
Third, a photoresist is formed to cover part of the first dielectric layer and then excess first dielectric layer is implanted by ions such as BF
2+
, B
3+
, F
−
, where photoresist does not cover these gaps.
Afterwards, rapid thermal process is employed to treat the first dielectric layer whereby SiOF molecules and B
2
O
5
molecules are formed on the surface of excess first dielectric layer.
Finally, a second dielectric layer is formed over the first dielectric layer wherein SiOF molecules improve step coverage of the second dielectric layer formation and B
2
O
5
molecules enhance fluidity of the second dielectric layer during formation of the second dielectric layer. Thus, not only is each gap totally filled by the second dielectric layer but also there is no void produced inside the second dielectric layer.
REFERENCES:
patent: 5489553 (1996-02-01), Chen
Huang Chien-Chung
Lai Yeong-Chih
Tsai Yu-Tai
Wu Huang-Hui
Hoang Quoc
Nelms David
United Microelectronics Corp.
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