Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2008-01-22
2008-01-22
Whitmore, Stacy (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C438S692000
Reexamination Certificate
active
11555314
ABSTRACT:
A method for identifying areas of low overburden which degrade (increase) metal polish nonuniformity is discussed. Also described is a method for modifying these areas to increase their overburden, thus slowing down the metal polish rate and improving overall polish uniformity. The resulting structure forms slots in groups of functional lines, such as bus lines, when the functional lines have a density prior to forming the slots that exceeds a predetermined amount. In one embodiment, an area of the wafer has a maximum width of 1.5 microns in an area that has a feature density greater than approximately 50 percent. The methods and resulting structures create a higher feature density, thereby increasing polishing uniformity.
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Construction Analysis, IBM power PC 750 RISC Microprocessor (copper) with TEM Analysis, Report No. SCA 9808-587, Integrated Circuit Engineering, Scottsdale, AZ, 3 pgs.
Aldrich Nathan A.
Tian Ruiqi
Travis Edward O.
Freescale Semiconductor Inc.
Vo Kim-Marie
Whitmore Stacy
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