Method of generating test patterns to efficiently screen...

Details Method of generating test patterns to efficiently screen... Method of generating test patterns to efficiently screen...

2008-07-01

2008-07-01

Louis-Jacques, Jacques (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S739000, C714S736000, C714S737000, C714S741000

Reexamination Certificate

active

11682914

ABSTRACT:
A methodology for generating scan based transition patterns (i.e., ATPG pattern generation for transition delay faults (“TDF”)) wherein when either a slow-to-rise (STR) or a slow-to-fall (STF) transition fault is detected, that specific fault is removed from a fault universe as well as its companion TDF, wherein the companion fault is a fault on the same node as the detected fault but has the opposite transition. In other words, if a slow-to-rise (STR) transition fault is detected, the slow-to-rise (STR) transition fault is removed from the fault universe as well as its corresponding slow-to-fall (STF) transition fault (and vise versa). By removing companion faults as well as those which are specifically detected, pattern generation run time is reduced as well as the total pattern count for the final delay test pattern.

REFERENCES:
patent: 7185254 (2007-02-01), Ishida et al.

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