Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-01-26
2001-12-25
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S739000
Reexamination Certificate
active
06334199
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of generating test patterns for a logic circuit, a system performing the method, and a computer readable medium instructing the system to perform the method; and especially relates to test pattern generation that divides a whole logic circuit into a plurality of partial circuits and generates test patterns for each of the partial circuits.
2. Related Art
Automatic Test Generation is an approach for defining faults that may occur in a circuit and for generating a test pattern automatically to detect the defined faults.
First, a random pattern used to detect the faults defined for the circuit is generated, and the generated random pattern is used to execute fault simulation for all the faults defined for the circuit.
Next, the pattern validated by fault simulation is used as a test pattern. A further random test pattern is generated such that the already detected faults will be no longer subjected to continued fault detection.
Once the number of faults detected by the random test pattern generation has decreased, a test pattern is generated by the ATG (Algorithmic Test Generation) process that algorithmically generates a test pattern while referencing the construction of the circuit. This time, the previsously detected faults also will no longer be subjected to fault detection.
This kind of conventional method is described in Japanese Patent Application Lail-Open No. 61-240173. The generation method described in the above publication uses a test pattern to detect faults having occurred in the whole of a logic circuit (hereinafter described as whole circuit). That is, the above generation method generates random numbers in a number corresponding to the input terminals of the whole circuit. Additionally, the above generation method generates a first test pattern using the generated random numbers.
In the ensuing fault detection for the logic circuit, the above first test pattern is applied to the input terminals of the above whole circuit. When fault detection using the first test pattern is saturated, the above generation method generates a second test pattern by using an algorithm such as D-algorithm for detecting a specific fault in the whole circuit. Faults which cannot be detected by the first test pattern are thereby detected using the second test pattern.
Thus, in the fault detection for a logic circuit, the use of test patterns generated in various ways allows an accurate fault detection.
To generate such test patterns two methods can be used: either a target fault detection rate (described below) is present so that processing is terminated when the fault detection rate reaches the set value; or the target fault detection rate is not set.
To calculate the fault detection rate, the following method can be used.
(1) (Fault detection rate)=(number of faults detected)/(total number of faults)
(2) (Fault detection rate)=(number of faults detected)/{(total number of faults)−(number of faults determined to be undetectable)}
(3) (Fault detection rate)={(number of faults detected)+(number of faults determined to be undetectable)}/(total number of faults)
The prior art described in the above publication has the following problems. That is, if the scale of a logic circuit, the object of fault detection, is large, the above first and second test patterns become complex. This causes a problem that it takes a long time to generate the first and second test patterns to satisfy a target fault detection rate.
Furthermore, since the first and second test patterns become large as they become complex, a storage device of a large capacity is required, for instance, for saving the first and second test patterns during the generation processes of these patterns, causing a restriction on the handling of the first and second patterns.
Still further, it is difficult to distribute the generated pattern to a plurality of processors. That is, the prior art method is difficult to apply to a distributed-processing test pattern generation system.
SUMMARY OF THE INVENTION
An object of the invention is to provide a novel method of generating test patterns for a logic circuit, a novel system performing the method, and a novel computer readable medium instructing the system to perform the method.
A further object of the invention is to provide a method of test pattern generation amendable to distributed processing.
These and other objects of the present invention will be apparent to those of skill in the art from the appended claims when read in light of the following specification and accompanying figures.
REFERENCES:
patent: 4366393 (1982-12-01), Kasuya
patent: 5513118 (1996-04-01), Dey et al.
patent: 6148425 (2000-11-01), Bhawmik et al.
patent: 61-240173 (1986-10-01), None
patent: 3-29870 (1991-02-01), None
patent: 5-142306 (1993-06-01), None
patent: 7-234266 (1995-09-01), None
Ono Toshinobu
Toumiya Tamaki
Amanze Emeka J.
De'cady Albert
NEC Corporation
Young & Thompson
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