Method of generating test pattern for integrated circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C714S738000, C714S728000, C714S745000

Reexamination Certificate

active

07024606

ABSTRACT:
A method for preventing the scale of a circuit from being extended and for preventing noise from being generated by a simultaneous value change in output buffers includes: the first process of checking the number of output buffers15A through15D whose output values change when boundary scan cells13E through13H output input patterns; the second process of checking the noise value generated by the change in the output values when all output values from the output buffers checked in the first process change; the third process of selecting the output buffer from the buffers checked in the first process such that the noise value checked in the second process can be within the noise allowable value; and the fourth process of outputting as a test pattern a pattern obtained by amending the input pattern such that the output value of the output buffer selected in the third process can change.

REFERENCES:
patent: 3949162 (1976-04-01), Malueg
patent: 5812561 (1998-09-01), Giles et al.
patent: 5831990 (1998-11-01), Queen et al.
patent: 6094069 (2000-07-01), Magane et al.
patent: 6189128 (2001-02-01), Asaka
patent: 402059679 (1989-12-01), None
patent: 401321562 (1990-02-01), None
Schilling et al. (Electronic Circuits: Discrete and Integrated, 1979; pp. 560-615).

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method of generating test pattern for integrated circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of generating test pattern for integrated circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of generating test pattern for integrated circuit will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3575584

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.