Method of generating test pattern for integrated circuit

Details Method of generating test pattern for integrated circuit Method of generating test pattern for integrated circuit

2006-04-04

2006-04-04

Lamarre, Guy J. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S738000, C714S728000, C714S745000

Reexamination Certificate

active

07024606

ABSTRACT:
A method for preventing the scale of a circuit from being extended and for preventing noise from being generated by a simultaneous value change in output buffers includes: the first process of checking the number of output buffers15A through15D whose output values change when boundary scan cells13E through13H output input patterns; the second process of checking the noise value generated by the change in the output values when all output values from the output buffers checked in the first process change; the third process of selecting the output buffer from the buffers checked in the first process such that the noise value checked in the second process can be within the noise allowable value; and the fourth process of outputting as a test pattern a pattern obtained by amending the input pattern such that the output value of the output buffer selected in the third process can change.

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Schilling et al. (Electronic Circuits: Discrete and Integrated, 1979; pp. 560-615).

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