Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2011-08-23
2011-08-23
Tabone, Jr., John J (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S025000, C714S724000, C714S726000, C714S729000, C714S735000, C714S744000, C716S108000, C716S112000, C702S108000, C702S117000, C702S124000, C702S185000, C324S500000, C324S528000, C324S535000, C324S762010
Reexamination Certificate
active
08006156
ABSTRACT:
Various exemplary embodiments provide methods and apparatuses for generating test conditions that efficiently detect delay faults while preventing overkill. According to an exemplary embodiment, i) test timing correcting block sets test timing faster than the actual operation timing of a logical circuit to be tested, ii) logical simulation block performs simulation by using delay times of signal paths corrected by adding minimum slack margin, and iii) when the simulation indicates that an end-side flip-flop cannot acquire data after an expected transition of logical value, masking block generates mask data that masks data held in the end-side flip-flop.
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Kawasaki Microelectronics Inc.
Oliff & Berridg,e PLC
Tabone, Jr. John J
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